View CLRC632_1028171.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
& I*CODE
CL RC632
Multiple Protocol Contactless Reader IC
Product Specification Revision 3.0 Confidential May 2003
Philips Semiconductors
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 3.1 3.2 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 5 5.1 5.1.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.3 5.4 5.4.1 5.4.2 5.4.3 6 6.1 6.2
CL RC632
GENERAL INFORMATION ..................................................................................................................7 Scope ....................................................................................................................................................7 General Description...............................................................................................................................7 Features ................................................................................................................................................8 Ordering Information .............................................................................................................................8 BLOCK DIAGRAM ...............................................................................................................................9 PINNING INFORMATION ...................................................................................................................10 Pin Configuration.................................................................................................................................10 Pin Description ....................................................................................................................................11 DIGITAL INTERFACE ........................................................................................................................13 Overview of Supported -Processor Interfaces ..................................................................................13 Automatic -Processor Interface Type Detection ...............................................................................13 Connection to Different -Processor Types ........................................................................................14 Separated Read/Write Strobe .............................................................................................................14 Common Read/Write Strobe ...............................................................................................................15 Common Read/Write Strobe and Hand-Shake Mechanism: EPP ......................................................16 SPI compatible interface .....................................................................................................................17 CL RC632 REGISTER SET ................................................................................................................20 CL RC632 Registers Overview ...........................................................................................................20 Register Bit Behaviour.........................................................................................................................22 Register Description ............................................................................................................................23 Page 0: Command and Status ............................................................................................................23 Page 1: Control and Status .................................................................................................................31 Page 2: Transmitter and Control .........................................................................................................38 Page 3: Receiver and Decoder Control ..............................................................................................44 Page 4: RF-Timing and Channel Redundancy ...................................................................................51 Page 5: FIFO, Timer and IRQ- Pin Configuration ...............................................................................58 Page 6: RFU........................................................................................................................................63 Page 7: Test Control ...........................................................................................................................64 CL RC632 Register Flags Overview ...................................................................................................68 Modes of Register Addressing ............................................................................................................72 Paging Mechanism..............................................................................................................................72 Dedicated Address Bus.......................................................................................................................72 Multiplexed Address Bus.....................................................................................................................72 MEMORY ORGANISATION OF THE EPROM .................................................................................73 Diagram of the EPROM Memory Organisation..................................................................................73 Product Information Field (Read Only)................................................................................................74
2
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.4.1 6.4.2 7 7.1 7.2 7.2.1 7.3 7.4 7.5 8 8.1 8.1.1 8.2 8.2.1 8.2.2 8.3 8.4 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.4 10 10.1 10.2
CL RC632
Register Initialisation Files (Read/Write) .............................................................................................75 Start Up Register Initialisation File (Read/Write).................................................................................75 Shipment Content of Start Up Register Initialisation File ....................................................................76 Register Initialisation File (Read/Write)...............................................................................................77 Content of ICODE1 and ISO15693 STart Up Register Values.........................................................78 Crypto1 Keys (Write Only)...................................................................................................................78 Key Format..........................................................................................................................................79 Storage of Keys in the EPROM .........................................................................................................79 FIFO BUFFER.....................................................................................................................................80 Overview..............................................................................................................................................80 Accessing the FIFO Buffer ..................................................................................................................80 Access Rules.......................................................................................................................................80 Controlling the FIFO-Buffer .................................................................................................................81 Status Information about the FIFO-Buffer ...........................................................................................81 Register Overview FIFO Buffer ...........................................................................................................82 INTERRUPT REQUEST SYSTEM .....................................................................................................83 Overview..............................................................................................................................................83 Interrupt Sources Overview.................................................................................................................83 Implementation of Interrupt Request Handling....................................................................................84 Controlling Interrupts and their Status.................................................................................................84 Accessing the Interrupt Registers .......................................................................................................84 Configuration of Pin IRQ .....................................................................................................................84 Register Overview Interrupt Request System .....................................................................................85 TIMER UNIT ........................................................................................................................................86 Overview..............................................................................................................................................86 Implementation of the Timer Unit ........................................................................................................87 Block Diagram .....................................................................................................................................87 Controlling the Timer Unit....................................................................................................................88 Timer Unit Clock and Period ...............................................................................................................88 Status of the Timer Unit.......................................................................................................................89 TimeSlotPeriod....................................................................................................................................89 Usage of the Timer Unit ......................................................................................................................90 Time-Out- and Watch-Dog-Counter ....................................................................................................90 Stop Watch ..........................................................................................................................................91 Programmable One-Shot Timer ..........................................................................................................91 Periodical Trigger ................................................................................................................................91 Register Overview Timer Unit .............................................................................................................92 POWER REDUCTION MODES ..........................................................................................................93 Hard Power Down ...............................................................................................................................93 Soft Power Down.................................................................................................................................93 3 Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
10.3 10.4 11 11.1 11.2 11.3 11.4 12 13 13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.4 14 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 15 15.1 15.2
CL RC632
Stand By Mode....................................................................................................................................94 Receiver Power Down.........................................................................................................................94 START UP PHASE .............................................................................................................................95 Hard Power Down Phase ....................................................................................................................95 Reset Phase........................................................................................................................................95 Initialising Phase .................................................................................................................................95 Initialising the Parallel Interface-Type .................................................................................................96 OSCILLATOR CIRCUITRY ................................................................................................................97 TRANSMITTER PINS TX1 AND TX2 .................................................................................................98 Configuration of TX1 and TX2.............................................................................................................98 Operating Distance versus Power Consumption ................................................................................99 Antenna Driver Output Source Resistance .........................................................................................99 Source Resistance Table ..................................................................................................................100 Formula for the Source Resistance...................................................................................................101 Calculating the Effective Source Resistance ....................................................................................101 Pulse Width .......................................................................................................................................102 RECEIVER CIRCUITRY ...................................................................................................................103 General..............................................................................................................................................103 Block Diagram ...................................................................................................................................103 Putting the Receiver into Operation ..................................................................................................104 Automatic Clock-Q Calibration ..........................................................................................................104 Amplifier.............................................................................................................................................105 Correlation Circuitry...........................................................................................................................106 Evaluation and Digitizer Circuitry ......................................................................................................106 SERIAL SIGNAL SWITCH ...............................................................................................................107 General..............................................................................................................................................107 Block Diagram ...................................................................................................................................107
15.3 Registers Relevant for the Serial Signal Switch................................................................................108 15.3.1 Active Antenna Concept....................................................................................................................109 15.3.2 Driving Two RF-Parts ........................................................................................................................109 16 17 18 18.1 18.2 MIFARE(R) HIGHER BAUDRATES ....................................................................................................110 ISO14443 B.......................................................................................................................................111 CL RC632 COMMAND SET .............................................................................................................112 General Description...........................................................................................................................112 General Behaviour ............................................................................................................................112
18.3 CL RC632 Commands Overview ......................................................................................................112 18.3.1 Basic States ......................................................................................................................................114 18.3.2 StartUp Command 3Fhex....................................................................................................................114 4 Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CL RC632
18.3.3 Idle Command 00hex ..........................................................................................................................114 18.4 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.5 18.5.1 18.5.2 18.5.3 18.5.4 18.5.5 Commands for ISO14443 A Card Communication ...........................................................................115 Transmit Command 1Ahex..................................................................................................................115 Receive Command 16hex ...................................................................................................................119 Transceive Command 1Ehex ..............................................................................................................122 States of the Card Communication ...................................................................................................122 State Diagram for the Card Communication .....................................................................................123 Commands for I*CODE1 and ISO15693 Label Communication ......................................................124 Transmit Command 1Ahex..................................................................................................................124 Receive Command 16hex ...................................................................................................................126 Transceive Command 1Ehex ..............................................................................................................128 States of the Label Communication ..................................................................................................128 State Diagram for the Label Communication ....................................................................................128
18.6 Commands to Access the EPROM..................................................................................................130 18.6.1 WriteE2 Command 01hex ...................................................................................................................130 18.6.2 ReadE2 Command 03hex ...................................................................................................................132 18.7 Diverse Commands...........................................................................................................................132 18.7.1 LoadConfig Command 07hex..............................................................................................................132 18.7.2 CalcCRC Command 12hex .................................................................................................................133 18.8 18.9 18.9.1 18.9.2 18.9.3 18.9.4 19 19.1 19.2 19.3 20 20.1 20.2 20.2.1 20.2.2 20.2.3 20.2.4 21 21.1 Error Handling during Command Execution......................................................................................134 MIFARE(R) Classic Security Commands.............................................................................................135 LoadKeyE2 Command 0Bhex .............................................................................................................135 LoadKey Command 19hex ..................................................................................................................135 Authent1 Command 0Chex .................................................................................................................136 Authent2 Command 14hex..................................................................................................................136 MIFARE CLASSIC AUTHENTICATION AND CRYPTO1..............................................................137 General..............................................................................................................................................137 Crypto1 Key Handling .......................................................................................................................137 Performing MIFARE Classic Authentication....................................................................................138 TYPICAL APPLICATION..................................................................................................................139 Circuit Diagram..................................................................................................................................139 Circuit Description .............................................................................................................................140 EMC Low Pass Filter.........................................................................................................................140 Antenna matching .............................................................................................................................140 Receiving Circuit ...............................................................................................................................141 Antenna Coil......................................................................................................................................141 TEST SIGNALS ................................................................................................................................142 General..............................................................................................................................................142
21.2 Measurements Using the Serial Signal Switch .................................................................................142 21.2.1 Tx-Control..........................................................................................................................................143 21.2.2 Rx-control ..........................................................................................................................................144 5 Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
21.3 21.4 21.5 21.6 22 22.1 22.2 22.3 22.4 22.4.1 22.4.2 22.4.3 22.5 22.5.1 22.5.2 22.5.3 23 24 25 25.1 26 26.1 26.2 27 27.1 27.2
CL RC632
Analog Test-Signals ..........................................................................................................................145 Digital Test-Signals ...........................................................................................................................146 Examples of ISO14443A Analog- and Digital Test Signals .............................................................147 Examples of I*CODE1 Analog- and Digital Test Signals ..................................................................148 ELECTRICAL CHARACTERISTICS ................................................................................................149 Absolute Maximum Ratings...............................................................................................................149 Operating Condition Range...............................................................................................................149 Current Consumption ........................................................................................................................149 Pin Characteristics ............................................................................................................................150 Input Pin Characteristics ...................................................................................................................150 Digital Output Pin Characteristics .....................................................................................................151 Antenna Driver Output Pin Characteristics .......................................................................................151 AC Electrical Characteristics .............................................................................................................152 AC Symbols.......................................................................................................................................152 AC Operating Specification ...............................................................................................................153 Clock Frequency ...............................................................................................................................157 EPROM CHARACTERISTICS ........................................................................................................158 ESD SPECIFICATION ......................................................................................................................159 PACKAGE OUTLINES .....................................................................................................................160 SO32 .................................................................................................................................................160 DISCLAIMERS..................................................................................................................................161 Life support applications....................................................................................................................161 Licence Policy ...................................................................................................................................161 REVISION HISTORY ........................................................................................................................162 Update from Revision 2.0 to Revision 3.0.........................................................................................162 Versions Up to Revision 3.0 ..............................................................................................................162
Contact Information......................................................................................................................................163
6
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
1 1.1 GENERAL INFORMATION Scope
CL RC632
This document describes the functionality of the CL RC632. It includes the functional and electrical specifications and gives details on how to design-in this device from system and hardware viewpoint.
1.2
General Description
The CL RC632 is member of a new family of highly integrated reader ICs for contactless communication at 13.56 MHz. This reader IC family utilises an outstanding modulation and demodulation concept completely integrated for all kinds of passive contactless communication methods and protocols at 13.56 MHz. The CL RC632 is pin- compatible to the MF RC500, the MF RC530, the MF RC531 and the SL RC 400. The CL RC632 supports all layers of the ISO14443 including the type A and type B communication scheme. The CL RC632 supports contactless communication using MIFARE(R) Higher Baudrates. The receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from ISO14443 compatible transponders. The digital part handles the complete ISO14443 framing and error detection (Parity & CRC). Additionally it supports the fast MIFARE(R) Classic security algorithm to authenticate MIFARE Classic (e.g. MIFARE(R) Standard, MIFARE(R) Light) products. The CL RC632 supports all layers of I*CODE1 and ISO 15693. The receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from I*CODE1 and ISO 15693 compatible transponders. The digital part handles I*CODE1 and ISO 15693 framing and error detection (CRC). The internal transmitter part is able to drive an antenna designed for proximity operating distance (up to 100 mm) directly without additional active circuitry. A comfortable parallel interface, which can be directly connected to any 8-bit -Processor gives high flexibility for the reader/terminal design. Additionally a SPI compatible interface is supported.
7
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
1.3 Features
CL RC632
* Highly integrated analog circuitry to demodulate and decode card/label response * Buffered output drivers to connect an antenna with minimum number of external components * Proximity operating distance (up to 100 mm) * Supports ISO 14443 A&B * Supports MIFARE(R) Dual Interface Card ICs and supports MIFARE(R) Classic protocol * Supports contactless communication with MIFARE(R) higher baudrates up to 424 kbaud * Supports I*CODE1 and ISO 15693 * Crypto1 and secure non-volatile internal key memory * Pin-compatible to the MF RC500, MF RC530, MF RC531 and the SL RC400 * Parallel -Processor interface with internal address latch and IRQ line * SPI compatible interface * Flexible interrupt handling * Automatic detection of parallel -Processor interface type * Comfortable 64 byte send and receive FIFO-buffer * Hard reset with low power function * Power down mode per software * Programmable timer * Unique serial number * User programmable start-up configuration * Bit- and byte-oriented framing * Independent power supply pins for digital, analog and transmitter part * Internal oscillator buffer to connect 13.56 MHz quartz, optimised for low phase jitter * Clock frequency filtering * 3.3 V to 5 V operation for transmitter (antenna driver) in short range and proximity applications * 3.3 V or 5V operation for the digital part 1.4 Ordering Information Type Number CL RC632 01T/0FE Package Name SO32 Description Small Outline Package; 32 leads Table 1-1: CL RC632 Ordering Information
8
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
2 BLOCK DIAGRAM
N_WR, N_RD, N_CS ALE A0, A1, A2 D0 to D7
CL RC632
Parallel Interface Control
(incl. Automatic Interface Detection & Synchronisation)
Voltage Monitor & Power On Detect State Machine Command Register Reset Control
DVDD
DVSS
FIFO Control
64 Byte FIFO
Programable Timer Control Register Bank Interrupt Control
Power Down Control
RSTPD
IRQ
EEPROM 32 x 16 Byte EEPROM Access Control
CRC16/CRC8 Generation & Check
Parallel/Seriell Converter Bit Counter Parity Generation & Check Cyrpto1 Unit Frame Generation & Check Bit Decoding 32 Bit Pseudo Random Generator Serial Data Switch
MFIN MFOUT
Master Key Buffer
Bit Coding
Level Shifters
Amplitude Rating Correlation and Bit Decoding Reference Voltage
Clock Generation, Filtering and Distribution
OSCIN
Oscillator
OSCOUT
Q-Clock Generation
Power On Detect
AVDD AVSS
Analog Test MUX
I-Channel Amplifier I-Channel Demodulator
Q-Channel Amplifier Q-Channel Demodulator
Transmitter Control
GND
V+
GND
V+
VMID
AUX
RX TVSS TX1 TX2 TVDD
Figure 1-1: CL RC632 Block Diagram
9
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
3 3.1 PINNING INFORMATION Pin Configuration
CL RC632
Pins denoted by bold letters are supplied by AVDD and AVSS. Pins drawn with bold lines are supplied by TVSS and TVDD. All other pins are supplied by DVDD and DVSS.
OSCIN IRQ MFIN MFOUT TX1 TVDD TX2 TVSS NCS NWR NRD DVSS D0 D1 D2 D3
1
32
OSCOUT RSTPD VMID RX AVSS AUX AVDD DVDD A2 A1 A0 ALE D7 D6 D5 D4
2
31
3
30
4
29
5
28
6
27
7
26
8
9
CL RC632 SO32
25
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
Figure 3-1: CL RC632 Pin Configuration for SO32 package
10
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
3.2 Pin Description O...Output;
TYPE I O I
CL RC632
Pin Types: I...Input;
PIN 1 2 3 SYMBOL OSCIN IRQ MFIN
PWR...Power
DESCRIPTION
Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 13.56 MHz). Interrupt Request: output to signal an interrupt event MIFARE Interface Input: accepts a digital, serial data stream according to ISO14443A (MIFARE) MIFARE Interface Output: delivers a serial data stream according to ISO14443A (MIFARE) I*CODE Interface Output: delivers a serial data stream according to I*CODE1 and ISO 15693 Transmitter 1: delivers the modulated 13.56 MHz energy carrier Transmitter Power Supply: supplies the output stage of TX1 and TX2 Transmitter 2: delivers the modulated 13.56 MHz energy carrier Transmitter Ground: supplies the output stage of TX1 and TX2 Not Chip Select: selects and activates the -Processor interface of the CL RC632 Not Write: strobe to write data (applied on D0 to D7) into the CL RC632 register Read Not Write: selects if a read or write cycle shall be performed. Not Write: selects if a read or write cycle shall be performed Not Read: strobe to read data from the CL RC632 register (applied on D0 to D7) Not Data Strobe: strobe for the read and the write cycle Not Data Strobe: strobe for the read and the write cycle Digital Ground Master In Slave Out (MISO), SPI interface, 8 Bit Bi-directional Data Bus 8 Bit Bi-directional Address and Data Bus Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. Address Strobe: strobe signal to latch AD0 to AD5 into the internal address latch when HIGH. Not Address Strobe: strobe signal to latch AD0 to AD5 into the internal address latch when LOW. Not Slave Select: strobe for the SPI communication Address Line 0: Bit 0 of register address Not Wait: signals with LOW that an access-cycle may started and with HIGH that it may be finished. Master Out Slave In, SPI interface
42 5 6 7 8 9 101
MFOUT TX1 TVDD TX2 TVSS NCS NWR R/NW nWrite NRD
O O PWR O PWR I I I I I I I PWR O I/O I/O I I I I I O I
11
1
NDS nDStrb DVSS D0 D0 to D7 AD0 to AD7 ALE
12 13 13 ... 201
211
AS nAStrb NSS A0
221
nWait MOSI
PIN Description (continued)
These pins offer different functionality according to the selected -Processor interface type. For detailed information, refer to chapter 4.
The SL RC400 uses the name SIGOUT for the MFOUT pin. The CLRC 632 functionality includes the test possibilities for the SL RC 400 using the pin MFOUT.
2
1
11
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
PIN 23 241 25 26 27 28 29 30 31 32 SYMBOL A1 A2 SCK DVDD AVDD AUX AVSS RX VMID RSTPD OSCOUT TYPE I I I PIWR PWR O PWR I PWR I O DESCRIPTION Address Line 1: Bit 1 of register address Address Line 2: Bit 2 of register address Serial Clock: Clock for the SPI interface Digital Power Supply Analog Power Supply
CL RC632
Auxiliary Output: This pin delivers analog test signals. The signal delivered on this output may be selected by means of the TestAnaOutSel Register. Analog Ground Receiver Input: Input pin for the cards response, which is the load modulated 13.56 MHz energy carrier, that is coupled out from the antenna circuit. Internal Reference Voltage: This pin delivers the internal reference voltage. Note: It has to be supported by means of a 100 nF block capacitor. Reset and Power Down: When HIGH, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a negative edge on this pin the internal reset phase starts. Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
Table 3-1: CL RC632 Pin Description
12
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
4 4.1 DIGITAL INTERFACE Overview of Supported -Processor Interfaces
CL RC632
The CL RC632 supports direct interfacing of various -Processors. Alternatively the Enhanced Parallel Port (EPP) of personal computers can be connected directly. The following table shows the parallel interface signals supported by the CL RC632:
Bus Control Signals Bus control Separated Read and Write Strobes address data control Common Read and Write Strobe address data control address data Separated Address and Data Bus NRD, NWR, NCS A0, A1, A2 D0 ... D7 R/NW, NDS, NCS A0, A1, A2 D0 ... D7 Multiplexed Address and Data Bus NRD, NWR, NCS, ALE AD0, AD1, AD2, AD3, AD4, AD5 AD0 ... AD7 R/NW, NDS, NCS, AS AD0, AD1, AD2, AD3, AD4, AD5 AD0 ... AD7 nWrite, nDStrb, nAStrb, nWait AD0, AD1, AD2, AD3, AD4, AD5 AD0 ... AD7
Common Read and Write Strobe with Handshake (EPP)
Table 4-1: Supported -Processor Interface Signals
4.2
Automatic -Processor Interface Type Detection
After every Power-On or Hard Reset, the CL RC632 also resets its parallel -Processor interface mode and checks the current -Processor interface type. The CL RC632 identifies the -Processor interface by means of the logic levels on the control pins after the Reset Phase. This is done by a combination of fixed pin connections (see below) and a dedicated initialisation routine (see 11.4).
13
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
4.3 Connection to Different -Processor Types
CL RC632
The connection to different -Processor types is shown in the following table:
Parallel Interface Type Separated Read/Write Strobe CL RC632 Dedicated Address Bus ALE A2 A1 A0 NRD NWR NCS D7 ... D0 HIGH A2 A1 A0 NRD NWR NCS D7 ... D0 Multiplexed Address Bus ALE LOW HIGH HIGH NRD NWR NCS AD7 ... AD0 Dedicated Address Bus HIGH A2 A1 A0 NDS R/NW NCS D7 ... D0 Multiplexed Address Bus AS LOW HIGH LOW NDS R/NW NCS AD7 ... AD0 Common Read/Write Strobe Multiplexed Address Bus with Handshake nAStrb HIGH HIGH nWait nDStrb nWrite LOW AD7 ... AD0
Table 4-2: Connection Scheme for Detecting the Parallel Interface Type
4.3.1
SEPARATED READ/WRITE STROBE
CL RC632
Address Bus (A3...An) Address Decoder
CL RC632
Non Multiplexed Address Address Decoder
NCS
NCS
LOW Address Bus (A0...A2)
A0...A2
HIGH HIGH
A2 A1 A0 D0...D7
Data Bus (D0...D7)
D0...D7
Multiplexed Address/Data (AD0...AD7)
HIGH
ALE NRD NWR
Address Latch Enable (ALE) Read Strobe (NRD) Write Strobe (NWR)
ALE NRD NWR
Read Strobe (NRD) Write Strobe (NWR)
Figure 4-1: Connection to -Processors with Separated Read/Write Strobes For timing specification refer to chapter 22.5.2.1.
14
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
4.3.2 COMMON READ/WRITE STROBE
CL RC632
CL RC632
Address Bus (A3...An) Address Decoder
CL RC632
Non Multiplexed Address Address Decoder
NCS
NCS
LOW Address Bus (A0...A2)
A0...A2
HIGH LOW
A2 A1 A0 D0...D7
Data Bus (D0...D7)
D0...D7
Multiplexed Address/Data (AD0...AD7)
HIGH
ALE NRD NWR
Address Strobe (AS)
ALE NRD NWR
Data Strobe (NDS) Read/Write (R/NW)
Data Strobe (NDS) Read/Write (R/NW)
Figure 4-2: Connection to -Processors with Common Read/Write Strobes
For timing specification refer to chapter 22.5.2.2.
15
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
4.3.3 COMMON READ/WRITE STROBE AND HAND-SHAKE MECHANISM: EPP
CL RC632
CL RC632
LOW
NCS
HIGH HIGH nWait
A2 A1 A0 D0...D7
Multiplexed Address/Data (AD1...AD8)
Address Strobe (nAStrb)
ALE NRD NWR
Data Strobe (nDStrb) Read/Write (nWrite)
Figure 4-3: Connection to -Processors with Common Read/Write Strobes and Hand-Shake
For timing specification refer to chapter 22.5.2.3. Remarks for EPP: Although in the standard for the EPP no chip select signal is defined, the N_CS of the CL RC632 allows inhibiting the nDStrb signal. If not used, it shall be connected to DVSS. After each Power-On or Hard Reset the nWait signal (delivered at pin A0) is high impedance. nWait will be defined at the first negative edge applied to nAStrb after the Reset Phase. The CL RC632 does not support Read Address Cycle.
16
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
4.4 SPI compatible interface
CL RC632
Additionally the serial peripheral interface (SPI) will be supported. The CL RC632 acts as a slave during the SPI communication. The SPI clock SCK has to be generated by the master. Data communication from the master to the slave uses the line MOSI. Line MISO is used to send data back from the CL RC632 to the master.
CL RC632 ALE A2 A1 A0 NRD NWR NCS D7 ... D1 D0 SPI Interface NSS SCK LOW MOSI HIGH HIGH LOW do not connect MISO
Table 4-3: SPI compatible interface
The following table shows the -Processor connection to the CL RC632 using the SPI interface.
CL RC632
LOW
NCS
SCK LOW MOSI MISO NSS
A2 A1 A0 D0 ALE
Figure 4-4: Connection to -Processors with SPI
17
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
Remarks for SPI: The implemented SPI interface is according to a standard SPI interface. The CL RC632 can only be addressed as a slave.
CL RC632
Read data: To read out data using the SPI interface the following structure has to be used. It is possible to read out up to n-data bytes. The first sent byte defines both, the mode itself and the address.
byte 0 MOSI MISO adr 0 XX
byte 1 adr 1 data 0
byte 2 adr. 2 data 1
........ ....... ......
byte n adr n data n-1
byte n+1 00 data n
The address byte has to fulfil the following format. The MSB bit of the first byte sets the used mode. To read data from the CL RC632 the MSB bit is set to 1. The bits 6-1 define the address and the last bit should be set to 0. According to scheme above, the last sent byte has been set to 0.
Address (MOSI) byte 0 byte 1 to byte n byte n+1
bit 7, MSB 1 RFU (0) 0
bit 6 - bit 1 address address 0
bit 0 RFU (0) RFU (0) 0
Write data: To write data to the CL RC632 using the SPI interface the following structure has to be used. It is possible to write out up to n-data bytes. The first send byte defines both, the mode itself and the address.
byte 0 MOSI MISO adr XX
byte 1 data 0 XX
byte 2 data 1 XX
.......... .......... ..........
byte n data n-1 XX
byte n+1 data n XX
The address byte has to fulfil the following format. The MSB bit of the first byte sets the used mode. To write data to the CL RC632 the MSB bit is set to 0. The bits 6-1 define the address and the last bit should be set to 0.
18
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
The SPI write mode writes all data to the same address as defined in byte 0. This allows an effective data writing to the CL RC632's FIFO buffer. Address line (MOSI) byte 0 byte 1 to byte n+1 MSB 0 bit 6 - bit 1 address data bit 0 RFU (0)
CL RC632
Note: The data bus pins D7...D1 have to be disconnected. For timing specification refer to chapter 22.5.2.4
19
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5 5.1
Page Page 0: Command and Status
CL RC632
CL RC632 REGISTER SET CL RC632 Registers Overview
Addresshex 0 1 2 3 4 5 6 7 8 9 A B C D E F Page 2: Transmitter and Coder Control 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Register Name Page Command FIFOData PrimaryStatus FIFOLength SecondaryStatus InterruptEn InterruptRq Page Control ErrorFlag CollPos TimerValue CRCResultLSB CRCResultMSB BitFraming Page TxControl CWConductance ModConductance CoderControl ModWidth ModWidthSOF TypeBFraming Page RxControl1 DecoderControl BitPhase RxThreshold BPSKDemControl RxControl2 ClockQControl Function selects the register page starts (and stops) the command execution in- and output of 64 byte FIFO buffer status flags of the receiver and transmitter and of the FIFO buffer number of bytes buffered in the FIFO diverse status flags control bits to enable and disable passing of interrupt requests interrupt request flags selects the register page diverse control flags e.g.: timer, power saving error flags showing the error status of the last command executed bit position of the first bit collision detected on the RF-interface actual value of the timer LSB of the CRC-Coprocessor register MSB of the CRC-Coprocessor register adjustments for bit oriented frames selects the register page controls the logical behaviour of the antenna driver pins TX1 and TX2 selects the conductance of the antenna driver pins TX1 and TX2 Defines the driver output conductance sets the clock rate and the coding mode selects the width of the modulation pulse selects the width of the modulation pulse for SOF (I*CODE Fast-Mode) Defines the framing for ISO14443-B communication selects the register page controls receiver behaviour controls decoder behaviour selects the bit-phase between transmitter and receiver clock selects thresholds for the bit decoder Control BPSK receiver behaviour controls decoder behaviour and defines the input source for the receiver controls clock generation for the 90 phase shifted Q-channel clock
CL RC632 Register Set (continued)
Page 3: Receiver and Decoder Control
Page 1: Control and Status
20
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
Page Page 4: RF-Timing and Channel Redundancy Addresshex 20 21 22 23 24 25 26 27 Page 5: FIFO, Timer and IRQ-Pin Configuration 28 29 2A 2B 2C 2D 2E 2F 30 31 32 Page 6: RFU 33 34 35 36 37 38 39 Page 7: Test Control 3A 3B 3C 3D 3E 3F Register Name Page RxWait ChannelRedundancy CRCPresetLSB CRCPresetMSB TimeSlotPeriod MFOUTSelect PreSet27 Page FIFOLevel TimerClock TimerControl TimerReload IRQPinConfig PreSet2E PreSet2F Page RFU RFU RFU RFU RFU RFU RFU Page RFU TestAnaSelect RFU RFU TestDigiSelect RFU RFU Function selects the register page
CL RC632
selects the time interval after transmission, before receiver starts selects the kind and mode of checking the data integrity on the RFchannel LSB of the pre-set value for the CRC register MSB of the pre-set value for the CRC register selects the time between automatically mitted Frames selects internal signal applied to pin MFOUT, includes the MSB of value TimeSlotPeriod see register 0x25 these values shall not be changed selects the register page defines level for FIFO over- and underflow warning selects the divider for the timer clock selects start and stop conditions for the timer defines the pre-set value for the timer configures the output stage of pin IRQ these values shall not be changed these values shall not be changed selects the register page reserved for future use reserved for future use reserved for future use reserved for future use reserved for future use reserved for future use reserved for future use selects the register page reserved for future use selects analog test mode reserved for future use reserved for future use selects digital test mode reserved for future use reserved for future use
Table 5-1: CL RC632 Register Overview
21
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.1.1 REGISTER BIT BEHAVIOUR
CL RC632
Bits and flags for different registers behave differently, depending on their functions. In principle bits with same behaviour are grouped in common registers.
Abbreviation
Behaviour read and write
Description These bits can be written and read by the -Processor. Since they are used only for control means, there content is not influenced by internal state machines, e.g. the TimerReload-Register may be written and read by the Processor. It will also be read by internal state machines, but never changed by them. These bits can be written and read by the -Processor. Nevertheless, they may also be written automatically by internal state machines, e.g. the CommandRegister changes its value automatically after the execution of the actual command. These registers hold flags, which value is determined by internal states only, e.g. the ErrorFlag-Register can not be written from external but shows internal states. These registers are used for control means only. They may be written by the Processor but can not be read. Reading these registers returns an undefined value, e.g. the TestAnaSelect-Register is used to determine the signal on pin AUX, but it is not possible to read its content.
r/w
dy
dynamic
r
read only
w
write only
Table 5-2: Behaviour of Register Bits and its Designation
22
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2 5.2.1 5.2.1.1 Register Description PAGE 0: COMMAND AND STATUS Page Register
CL RC632
Selects the register page. Name: Page Address: 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38 Reset value: 10000000, 0x80
7 UsePage Select Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 0 r/w
2
1 PageSelect
0
r/w
r/w
r/w
Description of the bits Bit 7 Symbol UsePageSelect Function If set to 1, the value of PageSelect is used as register address A5, A4, and A3. The LSBbits of the register address are defined by the address pins or the internal address latch, respectively. If set to 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Table 4-2. Reserved for future use. The value of PageSelect is used only if UsePageSelect is set to 1. In this case, it specifies the register page (which is A5, A4, and A3 of the register address).
6-3 2-0
0000 PageSelect
23
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.1.2 Command Register
CL RC632
Starts and stops the command execution. Name: Command 7 IFDetect Busy Access Rights r 6 0 r dy dy 5 Address: 0x01 4 3 Command dy dy dy dy Reset value:X0000000, 0xX0 2 1 0
Description of the bits Bit 7 Symbol IFDetectBusy Function Shows the status of Interface Detection Logic: Set to 0 means `Interface Detection finished successfully', Set to 1 signs `Interface Detection Ongoing'. Reserved for future use. Activates a command according the Command Code. Reading this register shows, which command is actually executed.
6 5-0
0 Command
24
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.1.3 FIFOData Register
CL RC632
In- and output of the 64 byte FIFO buffer. Name: FIFOData Address: 0x02 Reset value: XXXXXXXX, 0xXX
7 Access Rights dy
6 dy
5 dy
4 FIFOData dy
3 dy
2 dy
1 dy
0 dy
Description of the bits Bit 7-0 Symbol FIFOData Function Data input and output port for the internal 64 byte FIFO buffer. The FIFO buffer acts as parallel in/parallel out converter for all data stream in- and outputs.
25
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.1.4 PrimaryStatus Register
CL RC632
Status flags of the receiver, transmitter and the FIFO buffer. Name: PrimaryStatus 7 0 Access Rights r r 6 Address: 0x03 5 ModemState r r 4 3 IRq r Reset value: 00000101, 0x05 2 Err r 1 HiAlert r 0 LoAlert r
Description of the bits Bit 7 6-4 Symbol 0 ModemState Reserved for future use. ModemState shows the state of the transmitter and receiver state machines.
State 000 Name of State Idle Description Neither the transmitter nor the receiver is in operation, since none of them is started or since none of them has input data. Transmitting the `Start Of Frame' Pattern. Transmitting data from the FIFO buffer (or redundancy check bits). Transmitting the `End Of Frame' Pattern. Intermediate state, when receiver starts. Intermediate state, when receiver finishes. Waiting until the time period selected in the RxWait Register is expired. Receiver activated; Awaiting an input signal at pin Rx. Receiving data.
Function
001 010 011 100
TxSOF TxData TxEOF GoToRx1 GoToRx2
101 110 111
PrepareRx AwaitingRx Receiving
3 2 1
IRQ Err HiAlert
This bit shows, if any interrupt source requests attention (with respect to the setting of the interrupt enable flags in the InterruptEn Register). This bit is set to 1, if any error flag in the ErrorFlag Register is set. Is set to 1, when the number of bytes stored in the FIFO buffer fulfil the following equation: HiAlert = (64 - FIFOLength) WaterLevel
Example: FIFOLength=60, WaterLevel=4 FIFOLength=59, WaterLevel=4 HiAlert =1 HiAlert =0
0
LoAlert
Is set to 1, when the number of bytes stored in the FIFO buffer fulfil the following equation: LoAlert = FIFOLength WaterLevel
Example: FIFOLength=4, WaterLevel=4 FIFOLength=5, WaterLevel=4 LoAlert =1 LoAlert =0
26
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.1.5 FIFOLength Register
CL RC632
Number of bytes buffered in the FIFO. Name: FIFOLength Address: 0x04 Reset value: 00000000, 0x00
7 0 Access Rights r
6
5
4
3 FIFOLength
2
1
0
r
r
r
r
r
r
r
Description of the bits Bit 7 6-0 Symbol 0 FIFOLength Reserved for future use. Indicates the number of bytes stored in the FIFO buffer. Writing to the FIFOData Register increments, reading decrements FIFOLength. Function
27
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.1.6 SecondaryStatus Register
CL RC632
Diverse Status flags. Name: SecondaryStatus Address: 0x05 Reset value: 01100000, 0x60
7 TRunning Access Rights r
6 E2Ready r
5 CRCReady r
4 0 r
3 0 r
2 r
1 RxLastBits r
0 r
Description of the bits Bit 7 6 5 4-3 2-0 Symbol TRunning E2Ready CRCReady 00 RxLastBits Function If set to 1, the CL RC632's timer unit is running, e.g. the counter will decrement the Timer Value Register with the next timer clock. If set to 1, the CL RC632 has finished programming the E2PROM. If set to 1, the CL RC632 has finished calculating the CRC. Reserved for future use. Show the number of valid bits in the last received byte. If zero, the whole byte is valid.
28
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.1.7 InterruptEn Register
CL RC632
Control bits to enable and disable passing of interrupt requests. Name: InterruptEn Address: 0x06 Reset value: 00000000, 0x00
7 SetIEn Access Rights w
6 0 r/w
5 TimerIEn r/w
4 TxIEn r/w
3 RxIEn r/w
2 IdleIEn r/w
1 HiAlertIEn r/w
0 LoAlertIEn r/w
Description of the bits Bit 7 6 5 4 Symbol SetIEn 0 TimerIEn TxIEn Function Set to 1 SetIEn defines that the marked bits in the InterruptEn Register are set, Set to 0 clears the marked bits. Reserved for future use. Allows the timer interrupt request (indicated by bit TimerIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn. Allows the transmitter interrupt request (indicated by bit TxIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn. Allows the receiver interrupt request (indicated by bit RxIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn. Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn. Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn. Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn.
3 2 1
RxIEn IdleIEn HiAlertIEn
0
LoAlertIEn
29
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.1.8 InterruptRq Register
CL RC632
Interrupt request flags. Name: InterruptRq Address: 0x07 Reset value: 00000000, 0x00
7 SetIRq Access Rights w
6 0 r/w
5 TimerIRq dy
4 TxIRq dy
3 RxIRq dy
2 IdleIRq dy
1 HiAlertIRq dy
0 LoAlertIRq dy
Description of the bits Bit 7 Symbol SetIRq Function Set to 1, SetIRq defines that the marked bits in the InterruptRq Register are set. Set to 0 SetIRq defines, that the marked bits in the InterruptRq Register are cleared. Reserved for future use. Set to 1, when the timer decrements the TimerValue Register to zero. Set to 1, when one of the following events occurs: Transceive Command: All data transmitted. Auth1 and Auth2 Command: All data transmitted. WriteE2 Command: All data is programmed. CalcCRC Command: All data is processed. 3 2 RxIRq IdleIRq This bit is set to 1, when the receiver terminates. This bit is set to 1, when a command terminates by itself e.g. when the Command Register changes its value from any command to the Idle Command. If an unknown command is started bit IdleIRq is set. Starting the Idle Command by the -Processor does not set bit IdleIRq. This bit is set to 1, when bit HiAlert is set. In opposite to HiAlert, HiAlertIRq stores this event and can only be reset by means of bit SetIRq. This bit is set to 1, when bit LoAlert is set. In opposite to LoAlert, LoAlertIRq stores this event and can only be reset by means of bit SetIRq.
6 5 4
0 TimerIRq TxIRq
1 0
HiAlertIRq LoAlertIRq
30
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.2 5.2.2.1 PAGE 1: CONTROL AND STATUS Page Register
CL RC632
Selects the register page. See 5.2.1.1 Page Register.
5.2.2.2
Control Register
Diverse control flags, e.g.: timer, power saving. Name: Control Address: 0x09 Reset value: 00000000, 0x00
7 0 Access Rights r/w
6 0 r/w
5 StandBy dy
4 PowerDown dy
3 Crypto1On dy
2 TStopNow w
1 TStartNow w
0 FlushFIFO w
Description of the bits Bit 7-6 5 4 3 Symbol 00 StandBy PowerDown Crypto1On Reserved for future use Setting this bit to 1 enters the Soft PowerDown Mode. This means, internal current consuming blocks are switched off, the oscillator keeps running. Setting this bit to 1 enters the Soft PowerDown Mode. This means, internal current consuming blocks are switched off including the oscillator. This bit indicates that the Crypto1 unit is switched on and therefore all data communication with the card is encrypted. This bit can only be set to 1 by a successful execution of the Authent2 Command. Setting this bit to 1 stops the timer immediately. Reading this bit will always return 0. Setting this bit to 1 starts the timer immediately. Reading this bit will always return 0. Setting this bit to 1clears the internal FIFO-buffer's read- and write-pointer (FIFOLength becomes 0) and the flag FIFOOvfl immediately. Reading this bit will always return 0. Function
2 1 0
TStopNow TStartNow FlushFIFO
31
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.2.3 ErrorFlag Register
CL RC632
Error flags showing the error status of the last executed command. Name: ErrorFlag Address: 0x0A Reset value: 01000000, 0x40
7 0 Access Rights r
6 KeyErr r
5 AccessErr r
4 FIFOOvfl r
3 CRCErr r
2 FramingErr r
1 ParityErr r
0 CollErr r
Description of the bits Bit 7 6 Symbol 0 KeyErr Reserved for future use. This bit is set to 1, if the LoadKeyE2 or the LoadKey Command recognises, that the input data is not coded according to the Key format definition. This bit is set to 0 starting the LoadkeyE2 or the LoadKey command. This bit is set to 1, if the access rights to the EPROM are violated. This bit is set to 0 starting an EPROM related command. This bit is set to 1, if the -Processor or a CL RC632's internal state machine (e.g. receiver) tries to write data into the FIFO buffer although the FIFO buffer is already full. This bit is set to 1, if RxCRCEn is set and the CRC fails. It is cleared to 0 automatically at receiver start phase during the state PrepareRx. This bit is set to 1, if the SOF is incorrect. It is cleared automatically at receiver start (that is during the state PrepareRx). This bit is set to 1, if the parity check has failed. It is cleared automatically at receiver start (that is during the state PrepareRx). This bit is set to 1, if a bit-collision is detected. It is cleared automatically at receiver start (that is during the state PrepareRx). Note: only valid for communication according to ISO14443 A. Function
5 4
AccessErr FIFOOvfl
3 2 1 0
CRCErr FramingErr ParityErr CollErr
32
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.2.4 CollPos Register
CL RC632
Bit position of the first bit collision detected on the RF- interface. Name: CollPos Address: 0x0B Reset value: 00000000, 0x00
7 Access Rights r
6 r
5 r
4 CollPos r
3 r
2 r
1 r
0 r
Description of the bits Bit 7-0 Symbol CollPos Function This register shows the bit position of the first detected collision in a received frame. Example: 0x00 indicates a bit collision in the start bit 0x01 indicates a bit collision in the 1st bit 0x08 indicates a bit collision in the 8th bit Note: For ISO14443B a bit collision is not indicated in the CollPos register.
33
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.2.5 TimerValue Register
CL RC632
actual value of the timer. Name: TimerValue Address:0x0C Reset value: XXXXXXXX, 0xXX
7 Access Rights r
6 r
5 r
4 r
3 r
2 r
1 r
0 r
TimerValue
Description of the bits
Bit 7-0 Symbol TimerValue Function
This register shows the actual value of the timer counter.
34
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.2.6 CRCResultLSB Register
CL RC632
LSB of the CRC-Coprocessor register. Name: CRCResultLSB Address: 0x0D Reset value: XXXXXXXX, 0xXX
7 Access Rights r
6 r
5 r
4 r
3 r
2 r
1 r
0 r
CRCResultLSB
Description of the bits Bit 7-0 Symbol CRCResultLSB Function This register shows the actual value of the least significant byte of the CRC register. It is valid only if bit CRCReady is set to 1.
35
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.2.7 CRCResultMSB Register
CL RC632
MSB of the CRC-Coprocessor register. Name: CRCResultMSB Address: 0x0E Reset value: XXXXXXXX, 0xXX
7 Access Rights r
6 r
5 r
4 r
3 r
2 r
1 r
0 r
CRCResultMSB
Description of the bits Bit 7-0 Symbol CRCResultMSB Function This register shows the actual value of the most significant byte of the CRC register. It is valid only if bit CRCReady is set to 1. For 8-bit CRC calculation the registers value is undefined.
36
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.2.8 BitFraming Register
CL RC632
Adjustments for bit oriented frames. Name: BitFraming Address: 0x0F Reset value: 00000000, 0x00
7 0 Access Rights r/w
6 dy
5 RxAlign dy
4 dy
3 0 r/w
2 dy
1 TxLastBits dy
0 dy
Description of the bits Bit 7 6-4 Symbol 0 RxAlign Reserved for future use Used for reception of bit oriented frames: RxAlign defines the bit position for the first bit received to be stored in the FIFO. Further received bits are stored in the following bit positions. After reception, RxAlign is cleared automatically. Example: RxAlign = 0: RxAlign = 1: RxAlign = 7: the LSB of the received bit is stored at bit 0, second received bit is stored at bit position 1 the LSB of the received bit is stored at bit 1, second received bit is stored at bit position 2 the LSB of the received bit is stored at bit 7, second received bit is stored in the following byte at bit position 0 Function
3 2-0
0 TxLastBits
reserved for future use Used for transmission of bit oriented frames: TxLastBits defines the number of bits of the last byte that shall be transmitted. A 000 indicates that all bits of the last byte shall be transmitted. After transmission, TxLastBits is cleared automatically.
37
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.3 5.2.3.1 PAGE 2: TRANSMITTER AND CONTROL Page Register
CL RC632
Selects the register page. See 5.2.1.1 Page Register.
5.2.3.2
TxControl Register
Controls the logical behaviour of the antenna pin TX1 and TX2. Name: TxControl Address: 0x11 Reset value: 01011000, 0x58
7 0 Access Rights r/w
6
5
4 Force 100ASK r/w
3 TX2Inv r/w
2 TX2Cw r/w
1 TX2RFEn r/w
0 TX1RFEn r/w
ModulatorSource r/w r/w
Description of the bits Bit 7 6-5 Symbol 0 Modulator Source This value shall not be changed Selects the source for the modulator input: 00: 01: 10: 11: 4 3 2 Force100ASK TX2Inv TX2Cw LOW HIGH Internal Coder Pin MFIN Function
Set to 1, Force100ASK forces a 100% ASK Modulation independent of the setting in the ModConductance Register. Set to 1, the output signal on pin TX2 will deliver an inverted 13.56 MHz energy carrier. Set to 1, the output signal on pin TX2 will deliver continuously the un-modulated 13.56 MHz energy carrier. Setting TX2Cw to 0 enables modulation of the 13.56 MHz energy carrier. Set to 1, the output signal on pin TX2 will deliver the 13.56 MHz energy carrier modulated by the transmission data. If TX2RFEn is 0, TX2 drives a constant output level. Set to 1, the output signal on pin TX1 will deliver the 13.56 MHz energy carrier modulated by the transmission data. If TX1RFEn is 0, TX1 drives a constant output level.
1
TX2RFEn
0
TX1RFEn
38
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.3.3 CwConductance Register
CL RC632
Selects the conductance of the antenna driver pins TX1 and TX2. Name: CwConductance Address: 0x12 Reset value: 00111111, 0x3F
7 0 Access Rights r/w
6 0 r/w
5 r/w
4 r/w
3 GsCfgCW r/w
2 r/w
1 r/w
0 r/w
Description of the bits Bit 7-6 5-0 Symbol 00 GsCfgCW These values shall not be changed The value of this register defines the conductance of the output driver. This may be used to regulate the output power and subsequently current consumption and operating distance. Function
Note: For detailed information about GsCfgCW see 13.3
39
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.3.4 ModConductance Register
CL RC632
defines the driver output conductance.
Name: ModConductance
Address: 0x13
Reset value: 00111111, 0x03F
7 0 Access Rights r/w
6 0 r/w
5 r/w
4 r/w
3 GsCfgMod r/w
2 r/w
1 r/w
0 r/w
Description of the bits Bit 7-6 5-0 Symbol 00 GsCfgMod These values shall not be changed The value of this register defines the conductance of the output driver for the time of modulation. This may be used to regulate the modulation index. Function
Note: If Force100ASK is set to one, the value of GsCfgMod has no effect. For detailed information about GsCfgMod see 13.3
40
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.3.5 CoderControl Register
CL RC632
sets the clock rate and the coding mode Name: CoderControl Address:0x14 Reset value: 00011001, 0x19
7 SendOne Pulse Access Rights r/w
6 0 r/w
5
4 CoderRate
3
2
1 TxCoding
0
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7 Symbol SendOnePulse Function Set to 1, forces to generate only one Mudulation (for ISO 15693 only). This is used to switch to the next TimeSlot if the Inventory command is used. This bit is not cleared automatically, it has to be re-set to 0 by the user. These values shall not be changed This register defines the clock rate for Coder Circuit 000: 001: 010: 011: 100: 101: 110: 111: 2-0 TxCoding 000: 001: 010: 011: 100: 101: 110: 111: MIFARE(R) 848 kBaud MIFARE(R) 424 kBaud MIFARE(R) 212 kBaud MIFARE(R) 106 kBaud; ISO14443 A ISO 14443-B For ICODE1 standard mode and ISO 15693 (~52.97kHz) For ICODE1 fast mode (~26.48kHz) RFU NRZ according ISO14443-B MIFARE(R), ISO14443-A, (Miller coded) RFU RFU For ICODE1 standard mode (1 out of 256 coding) For ICODE1 fast mode (RZ coding) For ISO 15693 standard mode (1 out of 256 coding) For ISO 15693 fast mode (1 out of 4 coding)
6 5-3
0 CoderRate
This register defines the bit coding Mode and Framing during Transmission
41
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.3.6 ModWidth Register
CL RC632
selects the width of the modulation pulse. Name: ModWidth Address: 0x15 Reset value: 00010011, 0x13
7 Access Rights r/w
6 r/w
5 r/w
4 ModWidth r/w
3 r/w
2 r/w
1 r/w
0 r/w
Description of the bits Bit 7-0 Symbol ModWidth Function This register defines the width of the modulation pulse according to Tmod = 2(ModWidth +1) / fc.
5.2.3.7
ModWidthSOF Register Address: 0x16 Reset value: 00111111, 0x3F
Name: ModWidthSOF
7 Access Rights r/w
6 r/w
5 r/w
4 r/w
3 r/w
2 r/w
1 r/w
0 r/w
ModWidthSOF
Description of the bits Bit 7-0 Symbol ModWidthSOF Function This register defines the width of the modulation pulse for SOF Tmod = 2(ModWidth +1) / fc . Register setting: MIFARE(R) & ISO14443: 0x3F(Modulation width SOF: 9.44s). I*CODE1 Standard Mode: 0x3F (Modulation width SOF: 9.44s). I*CODE1 Fast Mode: 0x73 (Modulation width SOF: 18.88s). ISO 15693: 0x3F (Modulation width SOF: 9.44s).
42
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.3.8 TypeBFraming
CL RC632
defines the framing for ISO 14443 B communication Name: TypeBFraming 7 NoTx SOF Access Rights r/w 6 NoTx EOF r/w Address: 0x17 5 EOF Width r/w r/w 4 3 CharSpacing r/w r/w Reset value: 00111011, 0x3B 2 1 SOFWidth r/w r/w 0
Description of the bits Bit 7 6 5 4-2 1-0 Symbol NoTxSOF NoTXEOF EOFWidth CharSpacing SOFWidth Function Set to 1 TxCoder suppresses the SOF Set to 1 TxCoder suppresses the EOF 0: 1: 00: 01: 10: 11: Set the EOF to a length of 10 ETU Set the EOF to a length of 11 ETU Set the SOF to a length of 10 ETU LOW and 2 ETU HIGH Set the SOF to a length of 10 ETU LOW and 3 ETU HIGH Set the SOF to a length of 11 ETU LOW and 2 ETU HIGH Set the SOF to a length of 11 ETU LOW and 3 ETU HIGH
Set the length of the EGT length between 0 and 7 ETU.
43
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.4 5.2.4.1 PAGE 3: RECEIVER AND DECODER CONTROL Page Register
CL RC632
Selects the register page. See 5.2.1.1 Page Register.
5.2.4.2
RxControl1 Register
controls receiver behaviour. Name: RxControl1 Address: 0x19 Reset value: 01110011, 0x73
7 Access Rights r/w
6 SubCPulses r/w
5 r/w
4 r/w
3 r/w
2 LPOff r/w
1 Gain r/w
0 r/w
ISO Selection
Description of the bits Bit 7-5 Symbol SubCPulses Function Defines the number of subcarrier pulses per Bit 000: 1 Pulse 001: 2 Pulses 010: 4 Pulses 011: 8 Pulses ISO14443A&B 100: 16 Pulses I*CODE1 , ISO15693 101: RFU 110: RFU 111: RFU 00: 10: 01: 11: 2 1-0 LPOff Gain RFU ISO 14443 A&B
I*CODE1 , ISO15693
4-3
ISO Selection
RFU
Switches off a LowPassFilter at the internal amplifier. This register defines the receivers signal voltage gain factor: 00: 01: 10: 11: 20 dB 24 dB 31 dB 35 dB
44
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.4.3 DecoderControl Register
CL RC632
Controls decoder behaviour. Name: DecoderControl Address: 0x1A Reset value: 00001000, 0x08
7 0 Access Rights r/w
6 RxMultiple r/w
5 ZeroAfter Coll r/w
4 RxFraming r/w
3
2 RxInvert r/w
1 0 r/w
0 RxCoding r/w
r/w
Description of the bits Bit 7 6 5 4-3 Symbol 0 RxMultiple ZeroAfter Coll RxFraming Function These values shall not be changed If set to 0, after receiving of the Frame the receiver is deactivated If set to 1, it is possible to receive more than one Frame If set to 1, any bits received after a bit-collision are masked to zero. This eases resolving the anti-collision procedure defined in ISO14443-A. 00: 01: 10: 11: for I*CODE1 MIFARE(R), ISO14443A ISO 15693 ISO14443B
2 1 0
RxInvert 0 RxCoding
If set to 0, a modulation at the first half bit results a logic 1 (according I*CODE1) If set to 1, a modulation at the first half bit results a logic 0 (according ISO15693) These values shall not be changed 0: 1: Manchester Coding BPSK Coding
45
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.4.4 BitPhase Register
CL RC632
selects the bit-phase between transmitter and receiver clock. Name: BitPhase Address: 0x1B Reset value: 10101101, 0xAD
7 Access Rights r/w
6 r/w
5 r/w
4 BitPhase r/w
3 r/w
2 r/w
1 r/w
0 r/w
Description of the bits Bit 7-0 Symbol BitPhase Function Defines the phase relation between transmitter and receiver clock. Note: The correct value of this register is essential for proper operation.
46
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.4.5 RxThreshold Register
CL RC632
selects thresholds for the bit decoder. Name: RxThreshold Address: 0x1C Reset value: 11111111, 0xFF
7 Access Rights r/w
6 MinLevel r/w
5 r/w
4 r/w
3 r/w
2 CollLevel r/w
1 r/w
0 r/w
Description of the bits Bit 7-4 3-0 Symbol MinLevel CollLevel Function Defines the minimum signal strength at the decoder input that shall be accepted. If the signal strength is below this level, it is not evaluated. Defines the minimum signal strength at the decoder input that has to be reached by the weaker half-bit of the Manchester-coded signal to generate a bit-collision relatively to the amplitude of the stronger half-bit.
47
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.4.6 BPSKDemControl
CL RC632
controls BPSK demodulation Name: BPSKDemControl 7 NoRx SOF Access Rights r/w 6 NoRx EGT r/w Address: 0x1D 5 NoRx EOF r/w 4 Filter AmpDet r/w r/w 3 TauD r/w r/w Reset value: 00011110, 0x1E 2 1 TauB r/w 0
Description of the bits Bit 7 6 5 4 3-2 1-0 Symbol NoRxSOF NoRxEGT NoRxEOF FilterAmpDet TauD TauB Function If set to 1 a missing SOF in the receiving data stream will be ignored and no framing error indicated If set to 1 a too short or too long EGT in the receiving data stream will be ignored and no framing error indicated If set to 1 a missing EOF in the receiving data stream produces will be ignored and no framing error indicated Switches on a HighPassFilter for amplitude detection Change time-constant of internal PLL during data receiving Change time-constant of internal PLL during burst
48
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.4.7 RxControl2 Register
CL RC632
controls decoder behaviour and defines the input source for the receiver. Name:RxControl2 Address: 0x1E Reset value: 01000001, 0x41
7 RcvClkSelI Access Rights r/w
6 RxAutoPD r/w
5 0 r/w
4 0 r/w
3 0 r/w
2 0 r/w
1 r/w
0 r/w
DecoderSource
Description of the bits Bit 7 Symbol RcvClkSelI Function If set to 1, the I-clock is used for the receiver clock. Set to 0 indicates, that the Q-clock is used. I-clock and Q-clock are 90 phase shifted to each other If set to 1, the receiver circuit is automatically switched on before receiving and switched off afterwards. This may be used to reduce current consumption. If set to 0, the receiver is always activated. 5-2 1-0 0000 DecoderSource These values shall not be changed Selects the source for the decoder input: 00: 01: 10: 11: Low Internal Demodulator A subcarrier modulated Manchester coded signal at Pin MFIN A baseband Manchester coded signal at Pin MFIN
6
RxAutoPD
49
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.4.8 ClockQControl Register
CL RC632
controls clock generation for the 90 phase shifted Q-channel clock. Name: ClockQControl Address: 0x1F Reset value: 000XXXXX, 0xXX
7 ClkQ180Deg Access Rights r
6 ClkQCalib r/w
5 0 r/w
4 dy
3 dy
2 ClkQDelay dy
1 dy
0 dy
Description of the bits Bit 7 6 Symbol ClkQ180Deg ClkQCalib Function If the Q-clock is phase shifted more than 180 compared to the I-clock, the bit ClkQ180Deg is set to 1, otherwise it is 0. If this bit is 0, the Q-clock is calibrated automatically after the Reset Phase and after data reception from the card. If this bit is set to 1, no calibration is performed automatically. This value shall not be changed This register shows the number of delay elements actually used to generate a 90phase shift of the I-clock to obtain the Q-clock. It can be written directly by the -Processor or by the automatic calibration cycle.
5 4-0
0 ClkQDelay
50
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.5 5.2.5.1 PAGE 4: RF-TIMING AND CHANNEL REDUNDANCY Page Register
CL RC632
Selects the register page. See 5.2.1.1 Page Register.
5.2.5.2
RxWait Register
Selects the time interval after transmission, before receiver starts. Name: RxWait Address: 0x21 Reset value: 00000101, 0x06
7 Access Rights r/w
6 r/w
5 r/w
4 RxWait r/w
3 r/w
2 r/w
1 r/w
0 r/w
Description of the bits Bit 7-0 Symbol RxWait Function After data transmission, the activation of the receiver is delayed for RxWait bitclocks. During this `frame guard time' any signal at pin Rx is ignored.
51
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.5.3 ChannelRedundancy Register
CL RC632
Selects kind and mode of checking the data integrity on the RF-channel. Name: ChannelRedundancy Address: 0x22 Reset value: 00000011, 0x03
7 0 Access Rights r/w
6 0 r/w
5 CRC 3309 r/w
4 CRC8 r/w
3 RxCRCEn r/w
2 TxCRCEn r/w
1 ParityOdd r/w
0 ParityEn r/w
Description of the bits Bit 7-6 5 Symbol 00 CRC3309 This value shall not be changed If set to 1, CRC-calculation is done according ISO/IEC3309 (ISO14443B) and ISO 15693. Note: For usage according to ISO14443A this bit has to be 0. For usage according to I*CODE1 this bit has to be 0. 4 3 CRC8 RxCRCEn If set to 1, an 8-bit CRC is calculated. If set to 0, a 16-bit CRC is calculated. If set to 1, the last byte(s) of a received frame is/are interpreted as CRC byte/s. If the CRC itself is correct the CRC byte(s) is/are not passed to the FIFO. In case of an error, the CRCErr flag is set. If set to 0, no CRC is expected. If set to 1, a CRC is calculated over the transmitted data and the CRC byte(s) are appended to the data stream. If set to 0, no CRC is transmitted. If set to 1, an odd parity is generated or expected, respectively. If set to 0 an even parity is generated or expected, respectively. Note: For usage according to ISO14443-A this bit has to be 1. 0 ParityEn If set to 1, a parity bit is inserted in the transmitted data stream after each byte and expected in the received data stream after each byte (MIFARE(R), ISO14443A) If set to 0, no parity bit is inserted or expected (ISO14443B) Function
2
TxCRCEn
1
ParityOdd
52
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.5.4 CRCPresetLSB Register
CL RC632
LSB of the preset value for the CRC register. Name: CRCPresetLSB Address: 0x23 Reset value: 01010011, 0x63
7 Access Rights r/w
6 r/w
5 r/w
4 r/w
3 r/w
2 r/w
1 r/w
0 r/w
CRCPresetLSB
Description of the bits Bit 7-0 Symbol CRCPresetLSB Function CRCPresetLSB defines the starting value for CRC-calculation. This value is loaded into the CRC at the beginning of transmission, reception and the CalcCRC Command, if the CRC calculation is enabled. To use the ISO 15693 functionality the CRCPresetLSB Register has to be set to 0xFF.
53
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.5.5 CRCPresetMSB Register
CL RC632
MSB of the preset value for the CRC register. Name: CRCPresetMSB Address: 0x24 Reset value: 01010011, 0x63
7 Access Rights r/w
6 r/w
5 r/w
4 r/w
3 r/w
2 r/w
1 r/w
0 r/w
CRCPresetMSB
Description of the bits Bit 7-0 Symbol CRCPresetMSB Function CRCPresetMSB defines the starting value for CRC-calculation. This value is loaded into the CRC at the beginning of transmission, reception and the CalcCRC Command, if the CRC calculation is enabled. Note: This register is not relevant, if CRC8 is 1.
54
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.5.6 TimeSlotPeriod Register
CL RC632
defines the time slot period for I*CODE1 protocol. Name: TimeSlotPeriod 7 Access Rights r/w 6 r/w Address: 0x25 5 r/w 4 r/w 3 r/w Reset value: 00000000, 0x00 2 r/w 1 r/w 0 r/w
TimeSlotPeriod
Description of the bits Bit 7-0 Symbol
TimeSlotPeriod
Function TimeSlotPeriod defines the time between automatically transmitted Frames. To send a Quit-Frame according to the I*CODE1 protocol, it is necessary to have a relation to the beginning of the Command-Frame. The TimeSlotPeriod will start at the End of the Command transmission. For detailed information see also chapter 9.2.5
55
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.5.7 MFOUTSelect Register
CL RC632
Selects internal signal applied to pin MFOUT. Name: MFOUTSelect Address: 0x26 Reset value:00000000, 0x00
7 0
6 0
5 0
4 TimeSlot Period MSB r/w
3 0
2
1 MFOUTSelect
0
Access Rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7-5 4 3 2-0 Symbol 00000 TimeSlotPeriod MSB 0 MFOUTSelect These values shall not be changed MSB of value TimeSlotPeriod see register 0x25 These values shall not be changed MFOUTSelect defines which signal is routed to pin MFOUT. 000 001 010 011 100 Constant Low Constant High Modulation Signal (envelope) from internal coder, Miller coded Serial data stream, not Miller coded Output signal of the energy carrier demodulator (card modulation signal) Note: only valid MIFARE(R) and ISO14443 A at a baudrate of 106 kbaud. 101 Output signal of the subcarrier demodulator (Manchester coded card signal) Note: only valid MIFARE(R) and ISO14443 A at a baudrate of 106 kbaud. 110 111 RFU RFU Function
56
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.5.8 PreSet27 Register Address: 0x27 7 x Access Rights w 6 x w 5 x w 4 x w 3 x w
CL RC632
Name: PreSet27
Reset value: xxxxxxxx, 0xxx 2 x w 1 x w 0 x w
57
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.6 5.2.6.1 PAGE 5: FIFO, TIMER AND IRQ- PIN CONFIGURATION Page Register
CL RC632
Selects the register page. See 5.2.1.1 Page Register.
5.2.6.2
FIFOLevel Register
Defines the level for FIFO under- and overflow warning. Name: FIFOLevel Address: 0x29 Reset value:00001000, 0x08
7 0 Access Rights r/w
6 0 r/w
5 r/w
4 r/w
3 r/w
2 r/w
1 r/w
0 r/w
WaterLevel
Description of the bits Bit 7-6 5-0 Symbol 00 WaterLevel These values shall not be changed This register defines, the warning level of the CL RC632 for the -Processor for a FIFO-buffer over- or underflow: HiAlert is set to 1, if the remaining FIFO-buffer space is equal or less than WaterLevel bytes in the FIFO-buffer. LoAlert is set to 1, if equal or less than WaterLevel bytes are in the FIFO-buffer. Function
58
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.6.3 TimerClock Register
CL RC632
Selects the divider for the timer clock. Name: TimerClock Address: 0x2A Reset value: 00000111, 0x07
7 0 Access Rights r/w
6 0 r/w
5 TAutoRestart r/w
4 r/w
3 r/w
2 TPreScaler r/w
1 r/w
0 r/w
Description of the bits Bit 7-6 5 Symbol 00 TAutoRestart These values shall not be changed If set to 1, the timer automatically restart its count-down from TReloadValue, instead of counting down to zero. If set to 0 the timer decrements to zero and the bit TimerIRq is set to 1. Defines the timer clock fTimer. TPreScaler can be adjusted from 0 up to 21. The following formula is used to calculate fTimer : fTimer = 13.56 MHz / 2TPreScaler. Function
4-0
TPreScaler
59
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.6.4 TimerControl Register
CL RC632
Selects start and stop conditions for the timer. Name: TimerControl Address: 0x2B Reset value: 00000110, 0x06
7 0 Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 TStopRxEnd r/w
2 TStopRxBegin r/w
1 TStartTxEnd r/w
0 TStartTxBegin r/w
Description of the bits Bit 7-4 3 2 1 Symbol 0000 TStopRxEnd TStopRxBegin TStartTxEnd These values shall not be changed If set to 1, the timer stops automatically when data reception ends. 0 indicates, that the timer is not influenced by this condition. If set to 1, the timer stops automatically, when the first valid bit is received. 0 indicates, that the timer is not influenced by this condition. If set to 1, the timer starts automatically when data transmission ends. If the timer is already running, the timer restarts by loading TReloadValue into the timer. 0 indicates, that the timer is not influenced by this condition. If set to 1, the timer is starts automatically when the first bit is transmitted. If the timer is already running, the timer restarts by loading TReloadValue into the timer. 0 indicates, that the timer is not influenced by this condition. Function
0
TStartTxBegin
60
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.6.5 TimerReload Register
CL RC632
Defines the preset value for the timer. Name: TimerReload Address: 0x2C Reset value: 00001010, 0x0A
7 Access Rights r/w
6 r/w
5 r/w
4 r/w
3 r/w
2 r/w
1 r/w
0 r/w
TReloadValue
Description of the bits Bit 7-0 Symbol TreloadValue Function With a start event the timer loads with the TreloadValue. Changing this register affects the timer only with the next start event. If TReloadValue is set to 0, the timer cannot start.
61
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.6.6 IRQPinConfig Register
CL RC632
Configures the output stage for pin IRQ. Name: IRQPinConfig Address: 0x2D Reset value: 00000010, 0x02
7 0 Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 0 r/w
2 0 r/w
1 IRQInv r/w
0 IRQPushPull r/w
Description of the bits Bit 7-2 1 0 Symbol 000000 IRQInv IRQPushPull These values shall not be changed If set to 1, the signal on pin IRQ is inverted with respect to bit IRq. 0 indicates, that the signal on pin IRQ is equal to bit IRQ. If set to 1, pin IRQ works as standard CMOS output pad. 0 indicates, that pin IRQ works as open drain output pad. Function
5.2.6.7
PreSet2E Address: 0x2E 6 x w 5 x w 4 x w 3 x w Reset value: xxxxxxxx, 0xxx 2 x w 1 x w 0 x w
Name: PreSet2E 7 x Access Rights w
5.2.6.8
Preset2F Address: 0x2F 6 x w 5 x w 4 x w 3 x w Reset value: xxxxxxxx, 0xxx 2 x w 1 x w 0 x w
Name: PreSet2F 7 x Access Rights w
62
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.7 5.2.7.1 PAGE 6: RFU Page Register
CL RC632
Selects the register page. See 5.2.1.1 Page Register.
5.2.7.2
RFU Registers Address: 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 037 7 x 6 x r/w 5 x r/w 4 x r/w 3 x r/w Reset value:xxxxxxxx, 0xxx 2 x r/w 1 x r/w 0 x r/w
Name: RFU
Access Rights
r/w
Note: These registers are reserved for future use.
63
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.8 5.2.8.1 PAGE 7: TEST CONTROL Page Register
CL RC632
Selects the register page. See 5.2.1.1 Page Register.
5.2.8.2
RFU Register Address: 0x39 Reset value: xxxxxxxx, 0xxx
Name: RFU
7 x Access Rights w
6 x w
5 x w
4 x w
3 x w
2 x w
1 x w
0 x w
Note: This register is reserved for future use.
64
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.8.3 TestAnaSelect Register
CL RC632
Selects analog test signals. Name: TestAnaSelect Address: 0x3A Reset value: 00000000, 0x00
7 0 Access Rights w
6 0 w
5 0 w
4 0 w
3 w
2 w
1 w
0 w
TestAnaOutSel
Description of the bits Bit 7-4 3-0 Symbol 0000 TestAnaOutSel These values shall not be changed This register selects the internal analog signal that is routed to pin AUX. For detailed information see 21.3 Value 0 1 2 3 4 5 6 7 8 9 A B C D E F Signal Name Vmid Vbandgap VRxFollI VRxFollQ VRxAmpI VRxAmpQ VCorrNI VCorrNQ VCorrDI VCorrDQ VEvalL VEvalR VTemp RFU RFU RFU Function
65
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.8.4 RFU Register Address: 0x3B
CL RC632
Name: RFU
Reset value: xxxxxxxx, 0xxx
7 x Access Rights w
6 x w
5 x w
4 x w
3 x w
2 x w
1 x w
0 x w
Note: This register is reserved for future use.
5.2.8.5
RFU Register Address: 0x3C Reset value: xxxxxxxx, 0xxx
Name: RFU
7 x Access Rights w
6 x w
5 x w
4 x w
3 x w
2 x w
1 x w
0 x w
Note: This register is reserved for future use.
66
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.2.8.6 TestDigiSelect Register
CL RC632
Selects digital test mode. Name: TestDigiSelect Address:0x3D Reset value: xxxxxxxx, 0xxx
7 SignalTo MFOUT Access Rights w
6
5
4
3 TestDigiSignalSel
2
1
0
w
w
w
w
w
w
w
Description of the bits Bit 7 Symbol SignalToMFOUT Function Set to 1, overrules the setting in MFOUTSelect and the digital test signal defined in TestDigiSignalSel is routed to pin MFOUT instead. Set to 0, MFOUTSelect defines the signal delivered at pin MFOUT. Selects the digital test signal to be routed to pin MFOUT. For detailed information refer to chapter 21.4 TestDigiSignalSel F4hex E4hex D4hex C4hex B5hex A5hex 96hex 83hex E2hex 5.2.8.7 RFU Registers Address: 0x3E, 0x3F 7 x Access Rights w 6 x w 5 x w 4 x w 3 x w Reset value: xxxxxxxx, 0xxx 2 x w 1 x w 0 x w Signal Name s_data s_valid s_coll s_clock rd_sync wr_sync int_clock BPSK_out BPSK_sig
6-0
TestDigiSignalSel
Name: RFU
Note: These registers are reserved for future use.
67
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.3 CL RC632 Register Flags Overview Register ErrorFlag BitPhase TypeBFraming ClockQControl ClockQControl ClockQControl CoderControl ErrorFlag RxThreshold CollPos Command ChannelRedundancy ChannelRedundancy ErrorFlag CRCPresetLSB CRCPresetMSB SecondaryStatus CRCResultMSB CRCResultLSB Control RxControl2 SecondaryStatus TypeBFraming PrimaryStatus FIFOData FIFOLength ErrorFlag BPSKDemControl Control TxControl ErrorFlag RxControl1 CWConductance Address Register, Bit Position 0x0A, bit 5 0x1B, bits 7:0 0x17, bits 4:2 0x1F, bit 7 0x1F, bit 6 0x1F, bits 4:0 0x14, bits 5:3 0x0A, bit 0 0x1C, bits 3:0 0x0B, bits 7:0 0x01, bits 5:0 0x22, bit 5 0x22, bit 4 0x0A, bit 3 0x23, bits 7:0 0x24, bits 7:0 0x05 , bit 5 0x0E, bits 7:0 0x0D, bits 7:0 0x09, bit 3 0x1E, bits 1:0 0x05, bit 6 0x17, bit 5 0x03, bit 2 0x02, bits 7:0 0x04, bits 7:0 0x0A, bit 4 0x1D, bit 4 0x09, bit 0 0x11, bit 4 0x0A, bit 2 0x19, bits 1:0 0x12, bits 5:0
CL RC632
Flag(s) AccessErr BitPhase CharSpacing ClkQ180Deg ClkQCalib ClkQDelay CoderRate CollErr CollLevel CollPos Command CRC3309 CRC8 CRCErr CRCPresetLSB CRCPresetMSB CRCReady CRCResultMSB CRCResultLSB Crypto1On DecoderSource E2Ready EOFWidth Err FIFOData FIFOLength FIFOOvfl FilterAmpDet FlushFIFO Force100ASK FramingErr Gain GsCfgCW
68
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
Flag(s) GsCfgMod HiAlert HiAlertIEn HiAlertIRq IdleIEn IdleIRq IFDetectBusy Irq IRQInv IRQPushPull ISO Selection KeyErr LoAlert LoAlertIEn LoAlertIRq LPOff MFOUTSelect MinLevel ModemState ModulatorSource ModWidth NoRxEGT NoRxEOF NoRxSOF NoTxEOF NoTxSOF PageSelect ParityEn ParityErr ParityOdd PowerDown RcvClkSelI RxAlign Register ModConductance PrimaryStatus InterruptEn InterruptRq InterruptEn InterruptRq Command PrimaryStatus IRQPinConfig IRQPinConfig RxControl1 ErrorFlag PrimaryStatus InterruptEn InterruptRq RxControl1 MFOUTSelect RxThreshold PrimaryStatus TxControl ModWidth BPSKDemControl BPSKDemControl BPSKDemControl TypeBFraming TypeBFraming Page ChannelRedundancy ErrorFlag ChannelRedundancy Control RxControl2 BitFraming Address Register, Bit Position 0x13, bits 5:0 0x03, bit 1 0x06, bit 1 0x07, bit 1 0x06, bit 2 0x07, bit 2 0x01, bit 7 0x03, bit 3 0x2D, bit 1 0x2D, bit 0 0x19, bits 4:3 0x0A, bit 6 0x03, bit 0 0x06, bit 0 0x07, bit 0 0x19, bit 2 0x26, bits 2:0 0x1C, bits 7:4 0x03 , bit 6:4 0x11, bits 6:5 0x15, bits 7:0 0x1D, bit 6 0x1D, bit 5 0x1D, bit 7 0x17, bit 6 0x17, bit 7 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38, bits 2:0 0x22, bit 0 0x0A, bit 1 0x22 , bit 1 0x09, bit4 0x1E, bit 7 0x0F, bits 6:4
CL RC632
69
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
Flag(s) RxAutoPD RxCRCEn RxCoding RxFraming RxIEn RxIRq RxLastBits RxMultiple RxWait SetIEn SetIRq SignalToMFOUT SOFWidth StandBy SubCPulses TauB TauD TautoRestart TestAnaOutSel TestDigiSignalSel TimerIEn TimerIRq TimerValue TimeSlotPeriod TimeSlotPeriodMSB TpreScaler TReloadValue TRunning TstartTxBegin TstartTxEnd TstartNow TstopRxBegin TstopRxEnd TstopNow Register RxControl2 ChannelRedundancy DecoderControl DecoderControl InterruptEn InterruptRq SecondaryStatus DecoderControl RxWait InterruptEn InterruptRq TestDigiSelect TypeBFraming Control RxControl1 BPSKDemControl BPSKDemControl TimerClock TestAnaSelect TestDigiSelect InterruptEn InterruptRq TimerValue TimeSlotPeriod MFOUTSelect TimerClock TimerReload SecondaryStatus TimerControl TimerControl Control TimerControl TimerControl Control Address Register, Bit Position 0x1E, bit 6 0x22, bit 3 0x1A, bit 0 0x1A, bits 4:3 0x06, bit 3 0x07, bit 3 0x05, bits 2:0 0x1A,bit 6 0x21, bits 7:0 0x06, bit 67 0x07, bit 7 0x3D, bit 7 0x17, bits 1:0 0x09, bit 5 0x19, bits 7:5 0x1D, bits 1:0 0x1D, bits 3:2 0x2A, bit 5 0x3A, bits 6:4 0x3D, bit 6:0 0x06, bit 5 0x07, bit 5 0x0C, bits 7:0 0x25, bits 7:0 0x26, bit 4 0x2A, bits 4:0 0x2C, bits 7:0 0x05, bit 7 0x2B, bit 0 0x2B, bit 1 0x09, bit 1 0x2B, bit 2 0x2B, bit 3 0x09, bit 2
CL RC632
70
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
Flag(s) TX1RFEn TX2Cw TX2Inv TX2RFEn TxCoding TxCRCEn TxIEn TxIRq TxLastBits UsePageSelect WaterLevel ZeroAfterColl Register TxControl TxControl TxControl TxControl CoderControl ChannelRedundancy InterruptEn InterruptRq BitFraming Page FIFOLevel DecoderControl Address Register, Bit Position 0x11, bit 0 0x11, bit 3 0x11, bit 3 0x11, bit 1 0x14, bits 2:0 0x22, bit 2 0x06, bit 4 0x07, bit 4 0x0F, bits 2:0 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38, bit 7 0x29, bits 5:0 0x1A, bit 5
CL RC632
71
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
5.4 Modes of Register Addressing
CL RC632
Three mechanisms are valid to operate with the CL RC632: * * * Initiating functions and controlling data manipulation by executing commands Configuring electrical and functional behaviour via a set of configuration bits Monitoring the state of the CL RC632 by reading status flags
The commands, configuration bits and flags are accessed via the -Processor interface. The CL RC632 can internally address 64 registers. This basically requires six address lines.
5.4.1
PAGING MECHANISM
The CL RC632 register set is segmented into 8 pages with 8 register each. The Page-Register can always be addressed, no matter which page is currently selected.
5.4.2
DEDICATED ADDRESS BUS
Using the CL RC632 with dedicated address bus, the -Processor defines three address lines via the address pins A0, A1, and A2. This allows addressing within a page. To switch between registers in different pages the paging mechanism needs then to be used. The following table shows how the register address is assembled:
Register Bit: UsePageSelect Register-Address
1
PageSelect2
PageSelect1
PageSelect0
A2
A1
A0
Table 5-3: Dedicated Address Bus: Assembling the Register Address
5.4.3
MULTIPLEXED ADDRESS BUS
Using the CL RC632 with multiplexed address bus, the -Processor may define all 6 address lines at once. In this case either the paging mechanism or linear addressing may be used. The following table shows how the register address is assembled:
Interface Bus Type Multiplexed Address Bus (paging mode) Multiplexed Address Bus (linear addressing) Register Bit: UsePageSelect Register-Address
1 0
PageSelect2 AD5
PageSelect1 AD4
PageSelect0 AD3
AD2 AD2
AD1 AD1
AD0 AD0
Table 5-4: Multiplexed Address Bus: Assembling the Register Address
72
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
6 6.1 MEMORY ORGANISATION OF THE EPROM Diagram of the EPROM Memory Organisation
Block Address 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Byte Addresses 00 ... 0F 10 ... 1F 20 ... 2F 30 ... 3F 40 ... 4F 50 ... 5F 60 ... 6F 70 ... 7F 80 ... 8F 90 ... 9F A0 ... AF B0 ... BF C0 ... CF D0 ... DF E0 ... EF F0 ... FF 100 ... 10F 110 ... 11F 120 ... 12F 130 ... 13F 140 ... 14F 150 ... 15F 160 ... 16F 170 ... 17F 180 ... 18F 190 ... 19F 1A0 ... 1AF 1B0 ... 1BF 1C0 ... 1CF 1D0 ... 1DF 1E0 ... 1EF 1F0 ... 1FF Access Rights r r/w r/w r/w r/w r/w r/w r/w w w w w w w w w w w w w w w w w w w w w w w w w Keys for Crypto1 Register Initialisation File Memory Content Product Information Field
CL RC632
Block Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
See Also 6.2 6.3.1
Start Up Register Initialisation File
For User data or second Initialisation
6.3.3
6.4
Table 6-1: Diagram of EPROM Memory Organisation
73
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
6.2 Product Information Field (Read Only)
0 1 2 3 4 5 6 RFU 7 8 9 10 11 12 Internal 13
CL RC632
Byte Meaning
14 RsMaxP
15 CRC
Product Type Identification
Product Serial Number
Table 6-2: Product Information Field PRODUCT TYPE IDENTIFICATION: The CL RC632 is a member of a new family for highly integrated reader IC's. Each member of the product family has its unique Product Type Identification. The value of the Product Type Identification is shown in the table below:
Product Type Identification Byte Value 0 30hex 1 FFhex 2 FFhex 3 0Fhex 4 XXhex
Table 6-3: Product Type Identification Definition Byte 4 indicates the current version number. PRODUCT SERIAL NUMBER: The CL RC632 holds a four byte serial number that is unique for each device. INTERNAL: These 2 bytes hold internal trimming parameters.
RsMaxP: Maximum Source Resistance for the p-Channel Driver Transistor of pin TX1 and TX2 The source resistance of the p-channel driver transistors of pin TX1 and TX2 may be adjusted via the value GsCfgCW in the CWConductance Register (see chapter 13.3). The mean value of the maximum adjustable source resistance of the pins TX1 and TX2 is stored as an integer value in Ohms in byte RsMaxP. This value is denoted as maximum adjustable source resistance Rsref,max,p and is measured setting GsCfgCW in the Register CWConductance to 01hex. It is in the range between about 80 to 120 Ohm. CRC: The content of the product information field is secured via a CRC-byte, which is checked during start up.
74
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
6.3 Register Initialisation Files (Read/Write)
CL RC632
Register initialisation in the register address range from 10hex to 2Fhex is done automatically during the Initialising Phase (see 11.3), using the Start Up Register Initialisation File. Furthermore, the user may initialise the CL RC632 registers with values from the Register Initialisation File executing the LoadConfig-Command (see 18.7.1). Notes: * The Page-Register (addressed with 10hex, 18hex, 20hex, 28hex) is skipped and not initialised. * Make sure, that all PreSet registers are not changed. * Make sure, that all register bits that are reserved for future use (RFU) are set to 0.
6.3.1
START UP REGISTER INITIALISATION FILE (READ/WRITE)
The content of the EPROM memory bock address 1 and 2 are used to initialise the CL RC632 registers 10hex to 2Fhex during the Initialising Phase automatically. The default values written into the EPROM during production are shown chapter 6.3.2. The assignment is the following:
EPROM Byte Address 10hex (Block 1, Byte 0) 11hex ... 2Fhex (Block 2, Byte 15) Register Address 10hex 11hex ... 2Fhex Remark Skipped Copied ... Copied
Table 6-4: Byte Assignment for Register Initialisation at Start Up
75
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
6.3.2 SHIPMENT CONTENT OF START UP REGISTER INITIALISATION FILE
CL RC632
During production test, the Start Up Register Initialisation File is initialised with the values shown in the table below. With each power up these values are written into the CL RC632 register during the Initialising Phase.
EPROM Byte Address 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Reg. Address 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Value 00 58 3F 3F 19 13 3F 3B 00 73 08 AD FF 1E 41 00 00 06 03 63 63 00 00 00 00 08 07 06 0A 02 00 00 Page: free for user TxControl: Transmitter pins TX1 and TX2 switched off, bridge driver configuration, modulator driven from internal digital circuitry CwConductance: Source resistance of TX1 and TX2 to minimum. ModConductance: defines the output conductance CoderControl: ISO14443-A coding is set ModWidth: Pulse width for Miller pulse coding is set to standard configuration. ModWithSOF: Pulse width of SOF TypeFraming: ISO 14443-A framing is set Page: free for user RxControl1: ISO 14443-A is set and internal amplifier gain is maximum. DecoderControl: A bit-collision always evaluates to HIGH in the data bit stream. BitPhase: BitPhase is set to standard configuration. RxThreshold: MinLevel and CollLevel are set to maximum. BPSKDemControl: ISO14443-A is set RxControl2: Use Q-clock for the receiver, `Automatic Receiver Off' is switched on, decoder is driven from internal analog circuitry. ClockQControl: `Automatic Q-clock Calibration' is switched on. Page: free for user RxWait: Frame Guard Time is set to six bit clocks. ChannelRedundancy: Channel Redundancy is set according to ISO14443-A. CRCPresetLSB: CRC-Preset value is set according to ISO14443-A. CRCPresetMSB: CRC-Preset value is set according to ISO14443-A. TimeSlotPeriod: : defines the time for the ICODE1 time slots MFOUTSelect: Pin MFOUT is set to LOW. PreSet27 Page: free for user FIFOLevel: WaterLevel FIFO buffer warning level is set to standard configuration. TimerClock: TPreScaler is set to standard configuration, timer unit restart function is switched off. TimerControl: Timer is started at the end of transmission, stopped at the beginning of reception. TimerReload: TReloadValue: the timer unit preset value is set to standard configuration. IRQPinConfig: Pin IRQ is set to high impedance. PreSet2E PreSet2F Description
Table 6-5: Shipment Content of Start Up Configuration File Note: The default configuration of the CL RC632 supports the MIFARE(R) and ISO 14443 A communication scheme. The memory addresses 3 to 7 may be used for user specific initialisation files as ICODE1, ISO15693 or ISO14443 B.
76
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
6.3.3 REGISTER INITIALISATION FILE (READ/WRITE)
CL RC632
The content of the EPROM memory from block address 3 to 7 may be used to initialise the CL RC632 registers 10hex to 2Fhex by execution of the LoadConfig-Command (see 18.7.1). It requires a two bytes argument, used as the two bytes long EPROM starting byte address for the initialisation procedure. The assignment is the following:
EPROM Byte Address Starting Byte address for the EPROM Starting Byte address for the EPROM +1 ... Starting Byte address for the EPROM + 31 Register Address 10hex 11hex ... 2Fhex Remark Skipped Copied ... Copied
Table 6-6: Byte Assignment for Register Initialisation at Start Up
The Register Initialisation File is big enough to hold the values for two initialisation sets and leaves one more block (16 bytes) for the user. Note: The Register Initialisation File is read- and write-able for the user. Therefore, these bytes may also be used to store user specific data for other purposes. The standard configuration for the CL RC632 enables the MIFARE(R) and ISO14443 setting after each power up. To give the user the needed flexibility the startup configuration might be adapted and for example the ICODE1 start up configuration might be stored in the register block address 3 and 4.
77
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
6.3.4 CONTENT OF ICODE1 AND ISO15693 START UP REGISTER VALUES
CL RC632
To enable the ICODE1 functionality the following table gives an overview on the start up values for communication according t to the ICODE1 and ISO15693 scheme
EPROM Byte Address 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F Reg. Address 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Value 00 58 3F 05 2C 3F 3F 00 00 8B 00 54 68 00 41 00 00 08 0C FE FF 00 00 00 00 3E 0B 02 00 02 00 00 Page: free for user TxControl: Transmitter pins TX1 and TX2 switched off, bridge driver configuration, modulator driven from internal digital circuitry CwConductance: Source resistance of TX1 and TX2 to minimum. ModGsCfg: Source resistance of TX1 and TX2 at the time of Modulation, to determine the modulation index CoderControl: Selects the bit coding mode and the framing during transmission ModWidth: Pulse width for "used code (1 out of 256, RZ or 1 out of 4)" pulse coding is set to standard configuration. ModWidthSOF Pulse width of SOF TypeBFraming Page: free for user RxControl1: Amplifier gain is maximum. DecoderControl: A bit-collision always evaluates to HIGH in the data bit stream. BitPhase: BitPhase is set to standard configuration. RxThreshold: MinLevel and CollLevel are set to maximum. BPSKDemControl RxControl2: Use Q-clock for the receiver, `Automatic Receiver Off' is switched on, decoder is driven from internal analog circuitry. ClockQControl: Automatic Q-clock Calibration' is switched on. Page: free for user RxWait: Frame Guard Time is set to six bit clocks. ChannelRedundancy: Channel Redundancy is set according to ICODE1. CRCPresetLSB: CRC-Preset value is set according to ICODE1. CRCPresetMSB: CRC-Preset value is set according to ICODE1. TimeSlot Period : defines the time for the ICODE1 time slots MFOUTSelect: Pin MFOUT is set to LOW. PreSet27 Page: free for user FIFOLevel: WaterLevel: FIFO buffer warning level is set to standard configuration. TimerClock: TPreScaler is set to standard configuration, timer unit restart function is switched off. TimerControl: Timer is started at the end of transmission, stopped at the beginning of reception. TimerReload: TReloadValue: the timer unit preset value is set to standard configuration IRQPinConfig: Pin IRQ is set to high impedance. PreSet2E PreSet2F Description
Table 6-7: Content of ICODE1 Start Up Configuration
6.4
Crypto1 Keys (Write Only)
The MIFARE(R) Classic security requires specific keys to encrypt the communication on the contactless interface. These keys are named as crypto1 keys.
78
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
6.4.1 KEY FORMAT
CL RC632
To store a key in the EPROM, it has to be written in a specific format. Each key byte has to be split into the lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble). Each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. This format is a precondition for successful execution of the LoadKeyE2- (see 18.9.1) and the LoadKey-Command (see 18.9.2). With this format, 12 bytes of the EPROM memory are needed to store a 6 byte long key. This is shown in the following table:
Master Key Byte Master Key Bits EPROM Byte Address
Example
0 (LSB)
1
5 (MSB)
k7 k6 k5 k4 k7 k6 k5 k4 k3 k2 k1 k0 k3 k2 k1 k0
k7 k6 k5 k4 k7 k6 k5 k4 k3 k2 k1 k0 k3 k2 k1 k0 k7 k6 k5 k4 k7 k6 k5 k4 k3 k2 k1 k0 k3 k2 k1 k0
n 5Ahex
n+1 F0hex
n+2 5Ahex
n+3 E1hex
n+10 5Ahex
n+11 A5hex
Table 6-8: Key Storage Format Example: For the actual key A0 A1 A2 A3 A4 A5hex the value 5A F0 5A E1 5A D2 5A C3 5A B4 5A A5hex must be written into the EPROM. Note: Although it is possible to load data of any other format into the key storage location of the EPROM, it is not possible to obtain a valid card authentication with such a key. The LoadKeyE2-Command (see 18.9.1) will fail.
6.4.2
STORAGE OF KEYS IN THE EPROM
The CL RC632 reserves 384 bytes of memory area in the EPROM to hold Crypto1 keys. It uses no memory segmentation to mirror the 12 bytes structure of key storage. Thus, every byte of the dedicated memory area may be the start of a key. Example: If a key loading cycle starts at the last byte address of an EPROM block, e.g. key byte 0 is stored at 12Fhex, the following bytes are stored in the next EPROM block , e.g. key byte 1 is stored at 130hex, byte 2 at 131hex, up to byte 11 at 13Ahex. With 384 bytes of memory and 12 bytes needed for one key, 32 different keys may be stored in the EPROM. Note: It is not possible to load a key exceeding the EPROM byte location 1FFhex.
79
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
7 7.1 FIFO BUFFER Overview
CL RC632
An 8x64 bit FIFO buffer is implemented in the CL RC632 acting as a parallel-to-parallel converter. It buffers the input and output data stream between the -Processor and the internals of the CL RC632. Thus, it is possible to handle data streams with lengths of up to 64 bytes without taking timing constraints into account.
7.2 7.2.1
Accessing the FIFO Buffer ACCESS RULES
The FIFO-buffer input and output data bus is connected to the FIFOData Register. Writing to this register stores one byte in the FIFO-buffer and increments the internal FIFO-buffer write-pointer. Reading from this register shows the FIFO-buffer contents stored at the FIFO-buffer read-pointer and increments the FIFObuffer read-pointer. The distance between the write- and read-pointer can be obtained by reading the FIFOLength Register. When the -Processor starts a command, the CL RC632 may, while the command is in progress, access the FIFO-buffer according to that command. Physically only one FIFO-buffer is implemented, which can be used in input- and output direction. Therefore the -Processor has to take care, not to access the FIFO-buffer in an unintended way. The following table gives an overview on FIFO access during command processing:
Active Command StartUp Idle Transmit Receive Transceive WriteE2 ReadE2 LoadKeyE2 LoadKey Authent1 Authent2 LoadConfig CalcCRC The -Processor has to prepare the arguments, afterwards only reading is allowed -Processor has to know the actual state of the command (transmitting or receiving) -Processor is allowed to Write to FIFO Read from FIFO Remark
Table 7-1: Allowed Access to the FIFO-Buffer
80
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
7.3 Controlling the FIFO-Buffer
CL RC632
Besides writing to and reading from the FIFO-buffer, the FIFO-buffer pointers might be reset by setting the bit FlushFIFO. Consequently, FIFOLength becomes zero, FIFOOvfl is cleared, the actually stored bytes are not accessible anymore and the FIFO-buffer can be filled with another 64 bytes again.
7.4
Status Information about the FIFO-Buffer
The -Processor may obtain the following data about the FIFO-buffers status: * * * * Number of bytes already stored in the FIFO-buffer: FIFOLength Warning, that the FIFO-buffer is quite full: HiAlert Warning, that the FIFO-buffer is quite empty: LoAlert Indication, that bytes were written to the FIFO-buffer although it was already full: FIFOOvfl FIFOOvfl can be cleared only by setting bit FlushFIFO.
The CL RC632 can generate an interrupt signal * If LoAlertIRq is set to 1 it will activate Pin IRQ when LoAlert changes to 1. * If HiAlertIRq is set to 1 it will activate Pin IRQ when HiAlert changes to 1. The flag HiAlert is set to 1 if only WaterLevel bytes or less can be stored in the FIFO-buffer. It is generated by the following equation:
HiAlert = (64 - FIFOLength) WaterLevel
The flag LoAlert is set to 1 if WaterLevel bytes or less are actually stored in the FIFO-buffer. It is generated by the following equation:
LoAlert = FIFOLength WaterLevel
81
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
7.5 Register Overview FIFO Buffer
CL RC632
The following table shows the related flags of the FIFO buffer in alphabetic order.
Flags FIFOLength FIFOOvfl FlushFIFO HiAlert HiAlertIEn HiAlertIRq LoAlert LoAlertIEn LoAlertIRq WaterLevel
Register FIFOLength ErrorFlag Control PrimaryStatus InterruptIEn InterruptIRq PrimaryStatus InterruptIEn InterruptIRq FIFOLevel
Address Register, bit position 0x04, bits 6-0 0x0A, bit 4 0x09, bit 0 0x03, bit 1 0x06, bit 1 0x07, bit 1 0x03, bit 0 0x06, bit 0 0x07, bit 0 0x29, bits 5-0
Table 7-2. Registers associated with the FIFO Buffer
82
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
8 8.1 INTERRUPT REQUEST SYSTEM Overview
CL RC632
The CL RC632 indicates certain events by setting bit IRq in the PrimaryStatus-Register and, in addition, by activating pin IRQ. The signal on pin IRQ may be used to interrupt the -Processor using its interrupt handling capabilities. This allows the implementation of efficient -Processor software.
8.1.1
INTERRUPT SOURCES OVERVIEW
The following table shows the integrated interrupt flags, the related source and the condition for its setting. The interrupt flag TimerIRq indicates an interrupt set by the timer unit. The setting is done when the timer decrements from 1 either down to zero (TAutoRestart flag disabled) or to the TPreLoad value if TAutoRestart is enabled. The TxIRq bit indicates interrupts from different sources. If the transmitter is active and the state changes from sending data to transmitting the end of frame pattern, the transmitter unit sets automatically the interrupt bit. The CRC coprocessor sets TxIRq after having processed all data from the FIFO buffer. This is indicated by the flag CRCReady = 1. If the E2Prom programming has finished the TxIRq bit is set, indicated by the bit E2Ready = 1. The RxIRq flag indicates an interrupt when the end of the received data is detected. The flag IdleIRq is set if a command finishes and the content of the command register changes to idle. The flag HiAlertIRq is set to 1 if the HiAlert bit is set to one, that means the FIFO buffer has reached the level indicated by the bit WaterLevel, see chapter 7.4. The flag LoAlertIRq is set to 1 if the LoAlert bit is set to one, that means the FIFO buffer has reached the level indicated by the bit WaterLevel, see chapter 7.4.
Interrupt Flag TimerIRq
Interrupt Source Timer Unit Transmitter
Is set automatically, when the timer counts from 1 to 0 a data stream, transmitted to the card, ends all data from the FIFO buffer has been processed all data from the FIFO buffer has been programmed a data stream, received from the card, ends a command execution finishes the FIFO-buffer is getting full the FIFO-buffer is getting empty
TxIRq
CRC-Coprocessor EPROM
RxIRq IdleIRq HiAlertIRq LoAlertIRq
Receiver Command Register FIFO-buffer FIFO-buffer
Table 8-1: Interrupt Sources
83
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
8.2 8.2.1 Implementation of Interrupt Request Handling CONTROLLING INTERRUPTS AND THEIR STATUS
CL RC632
The CL RC632 informs the -Processor about the interrupt request source by setting the according bit in the InterruptRq Register. The relevance of each interrupt request bit as source for an interrupt may be masked with the interrupt enable bits of the InterruptEn Register.
Register InterruptEn InterruptRq Bit 7 SetIEn SetIRq Bit 6 rfu rfu Bit 5 TimerIEn TimerIRq Bit 4 TxIEn TxIRq Bit 3 RxIEn RxIRq Bit 2 IdleIEn IdleIRq Bit 1 HiAlertIEn HiAlertIRq Bit 0 LoAlertIEn LoAlertIRq
Table 8-2: Interrupt Control Registers If any interrupt request flag is set to 1 (showing that an interrupt request is pending) and the corresponding interrupt enable flag is set the status flag IRq in the PrimaryStatus Register is set to 1. Furthermore different interrupt sources can be set active simultaneously. Therefore, all interrupt request bits are `OR'ed and connected to the flag IRq and forwarded to pin IRQ.
8.2.2
ACCESSING THE INTERRUPT REGISTERS
The interrupt request bits are set automatically by the internal state machines of the CL RC632. Additionally the -Processor has access in order to set or to clear them. A special implementation of the InterruptRq and the InterruptEn Register allows the change a single bit status without influencing the other ones. If a specific interrupt register shall be set to one, the bit SetIxx has to be set to 1 and simultaneously the specific bit has to be set to 1 too. Vice versa, if a specific interrupt flag shall be cleared, a zero has to be written to the SetIxx and simultaneously the specific address of the interrupt register has to be set to 1. If a bit content shall not be changed during the setting or clearing phase a zero has to be written to the specific bit location. Example: writing 3Fhex to the InterruptRq Register clears all bits as SetIRq in this case is set to 0 and all other bits are set to 1. Writing 81hex sets bit LoAlertIRq to 1 and leaves all other bits untouched.
8.3
Configuration of Pin IRQ
The logic level of the status flag IRq is visible at pin IRQ. In addition, the signal on pin IRQ may be controlled by the following bits of the IRQPinConfig Register: * * IRQInv: if set to 0, the signal on pin IRQ is equal to the logic level of bit IRq. If set to 1, the signal on pin IRQ is inverted with respect to bit IRq. IRQPushPull: if set to 1, pin IRQ has standard CMOS output characteristics otherwise it is an open drain output and an external resistor is necessary to achieve a HIGH level at this pin.
Note: During the Reset Phase (see 11.2) IRQInv is set to 1 and IRQPushPull to 0. This results in a high impedance at pin IRQ.
84
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
8.4 Register Overview Interrupt Request System
CL RC632
The following table shows the related flags of the Interrupt Request System in alphabetic order.
Flags HiAlertIEn HiAlertIRq IdleIEn IdleIRq IRq IRQInv IRQPushPull LoAlertIEn LoAlertIRq RxIEn RxIRq SetIEn SetIRq TimerIEn TimerIRq TxIEn TxIRq
Register InterruptEn InterruptRq InterruptEn InterruptRq PrimaryStatus IRQPinConfig IRQPinConfig InterruptEn InterruptRq InterruptEn InterruptRq InterruptEn InterruptRq InterruptEn InterruptRq InterruptEn InterruptRq
Address Register, bit position 0x06, bit 1 0x07, bit 1 0x06, bit 2 0x07, bit 2 0x03, bit 3 0x07, bit 1 0x07, bit 0 0x06, bit 0 0x07, bit 0 0x06, bit 3 0x07, bit 3 0x06, bit 7 0x07, bit 7 0x06, bit 5 0x07, bit 5 0x06, bit 4 0x07, bit 4
Table 8-3 Registers associated with the Interrupt Request System
85
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
9 9.1 TIMER UNIT Overview
CL RC632
A timer is implemented in the CL RC632. It derives its clock from the 13.56 MHz chip-clock. The -Processor may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations: * * * * * Timeout-Counter Watch-Dog Counter Stop Watch Programmable One-Shot Periodical Trigger
The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. The timer can be triggered by events which will be explained in the following, but the timer itself does not influence any internal event (e.g. A timeout during data receiving does not influence the receiving process automatically). Furthermore, several timer related flags are set and these flags can be used to generate an interrupt.
86
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
9.2 9.2.1 Implementation of the Timer Unit BLOCK DIAGRAM
CL RC632
The following block diagram shows the timer module.
TStartTxBegin TxBegin Event TStartTxEnd TxEnd Event TAutoRestart TStartNow
QS
TReloadValue [7:0]
parallel in start counter / parallel load
TRunning TStopNow
Q
R
stop counter RxEnd Event TStopRxEnd RxBegin Event TStopRxBegin Counter Module (x <= x-1)
TPreScaler [4:0]
13.56 MHz
Clock Divider
>clock parallel out
to Parallel Interface
TimerValue [7:0]
Counter = 0 ?
to Interrupt Logic: TimerIRq
Figure 9-1: Timer Module Block Diagram The timer unit is designed in a way, that several events in combination with enabling flags start or stop the counter. For example, setting the bit TStartTxBegin to 1 enables to control the receiving of data using the timer unit. In addition, the first received bit is indicated by TxBeginEvent. This combination starts the counter at the defined TReloadValue. The timer stops either automatically if the counter value is equal to zero, or if a defined stop event happens.
87
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
9.2.2 CONTROLLING THE TIMER UNIT
CL RC632
The main part of the timer unit is a down-counter. As long as the down-counter value is unequal zero, it decrements its value with each timer clock. If TAutoRestart is enabled the timer does not decrement down to zero. Having reached the value 1 the timer reloads with the next clock with the TimerReload value. The timer is started immediately by loading a value from the TimerReload Register into the counter module. This may be triggered by one of the following events: * * * Transmission of the first bit to the card (TxBegin Event) and bit TStartTxBegin is 1 Transmission of the last bit to the card (TxEnd Event) and bit TStartTxEnd is 1 Bit TStartNow is set to 1 (by the -Processor)
Note: Every start event reloads the timer from the TimerReload Register. Thus, the timer unit is re-triggered. The timer can be configured to stop with one of the following events: * * * * Reception of the first valid bit from the card (RxBegin Event) and bit TStopRxBegin is set to 1 Reception of the last bit from the card (RxEnd event) and bit TStopRxEnd is set to 1 The counter module has decrement down to zero and bit TAutoRestart is set to 0 Bit TStopNow is set to 1 (by the -Processor)
Loading a new value, e.g. zero, into the TimerReload Register does not immediately influence the counter, since the TimerReload Register affects the counter units content only with the next start event. Thus, the TimerReload Register may be changed even if the timer unit is already counting. The consequence of changing the TimerReload Register will be visible after the next start event. If the counter is stopped by setting bit TstopNow, no TimerIRq is signalled.
9.2.3
TIMER UNIT CLOCK AND PERIOD
The clock of the timer unit is derived from the 13.56 MHz chip clock via a programmable divider. The clock selection is done with the TPreScaler Register that defines the timer unit clock frequency according to the following formula:
TTimerClock =
1
f TimerClock
2T Pr eScaler = 13.56MHz
The possible values for the TPreScaler Register range from 0 up to 21 resulting in minimum time TTimerClock of about 74 ns up to about 150 ms. The time period elapsed since the last start event is calculated with
TTimer =
TReLoadValue - TimerValue f TimerClock
resulting in a minimum time TTimer of about 74 ns up to about 40 s.
88
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
9.2.4 STATUS OF THE TIMER UNIT
CL RC632
The TRunning bit in the SecondaryStatus Register shows the timer's current status. Any configured start event starts the timer at the TReloadValue and changes the status flag TRunning to 1, any configured stop event stops the timer and sets the status flag TRunning back to 0. As long as status flag TRunning is set to 1, the TimerValue Register changes with the next timer unit clock. The actual timer unit content can be read directly via the TimerValue Register.
9.2.5
TIMESLOTPERIOD
For sending of I*CODE1-Quit-Frames it is necessary to generat a exact chronological relation to the begin of the command frame. Is TimeSlotPeriod > 0, with the end of command transmission the TimeSlotPeriod starst. If there are Data in the FIFO after reaching the end of TimeSlotPeriod, these data were sent at that moment. If the FIFO is empty nothing happens. As long as the contend of TimeSlotPeriod is > 0 the counter for the TimeSlotPeriod will start automatically after reaching the end. This allows a exact time relation to the end (as well as to the beginning) of the command frame for the generation and sending of the I*CODE1-Quit-Frames Is TimeSlotPeriod > 0 the next Frame starts exact with the interval TimeSlotPeriod/CoderRate delayed after each previous Send Frame. CoderRate defines the clock frequency of the coder. If TimeSlotPeriod = 0, the send function will not be triggered automatically. The content of the register TimeSlotPeriod can be changed during the active mode. The modification take effect at the next restart of the TimeSlotPeriod.
89
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
Example: CoderRate = 0x05 (~52.97kHz) For I*CODE1 standard mode the interval should be 8.458ms
CL RC632
->TimeSlotPeriod = CoderRate * interval = 52.97kHz * 8.458ms -1 = 447 (447 = 0x1BF) Note: The MSB of the TimeSlotPeriod is in the MFOUTSelect register.
Command
Quit1
Quit2
Response1
Response2
TSP1
TSP2
TimeSlotPeriod for TSP1 I*CODE1 Standard Mode I*CODE1 Fast Mode 0xBF 0x5F
TimeSlotPeriod for TSP2 0x1BF 0x67
Note: It is strictly recommended that bit TxCRCEn is set to 0 before the Quit-Frame is sent. If the TxCRCEn is not set to 0 a CRC value is calculated and sent with the Quit-Frame. To calculate the Quit value a CRC8 algorithm has to be used.
9.3 9.3.1
Usage of the Timer Unit TIME-OUT- AND WATCH-DOG-COUNTER
Having started the timer by setting TReloadValue the timer unit decrements the TimerValue Register beginning with a certain start event. If a certain stop event occurs e.g. a bit is received from the card, the timer unit stops (no interrupt is generated). On the other hand, if no stop event occurs, e.g. the card does not answer in the expected time, the timer unit decrements down to zero and generates a timer interrupt request. This signals the -Processor that the expected event has not occurred in the given time TTimer.
90
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
9.3.2 STOP WATCH
CL RC632
The time TTimer between a certain start- and stop event may be measured by the -Processor by means of the CL RC632 timer unit. Setting TReloadValue the timer starts to decrement. If the defined stop event occurs the timers stops. The time between start and stop can be calculated by
T = (T Re load value - Timervalue )* TTimer
if the timer does not decrements down to zero.
9.3.3
PROGRAMMABLE ONE-SHOT TIMER
The -Processor starts the timer unit and waits for the timer interrupt. After the specified time TTimer the interrupt will occur.
9.3.4
PERIODICAL TRIGGER
If the -Processor sets bit TAutoRestart, it will generate an interrupt request periodically after every TTimer.
91
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
9.4 Register Overview Timer Unit
CL RC632
The following table shows the related flags of the Timer Unit in alphabetic order.
Flags TautoRestart TimerValue TimerReloadValue TpreScaler Trunning TstartNow TstartTxBegin TstartTxEnd TstopNow TstopRxBegin TstopRxEnd
Register TimerClock TimerValue TimerReload TimerClock SecondaryStatus Control TimerControl TimerControl Control TimerControl TimerControl
Address 0x2A, bit 5 0x0C, bits 7-0 0x2C, bits 7-0 0x2A, bits 4-0 0x05, bit 7 0x09, bit 1 0x2B, bit 0 0x2B, bit 1 0x09, bit 2 0x2B, bit 2 0x2B, bit 3
Table 9-1 Registers associated with the Timer Unit
92
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
10 POWER REDUCTION MODES
CL RC632
10.1 Hard Power Down A Hard Power Down is enabled with HIGH on pin RSTPD. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself). The output pins are frozen at a certain value. This is shown in the following table.
SYMBOL OSCIN IRQ MFIN MFOUT TX1 PIN 1 2 3 4 5 TYPE I O I O O DESCRIPTION Not separated from input, pulled to AVSS High impedance Separated from Input LOW HIGH, if TX1RFEn=1 LOW, if TX1RFEn=0 HIGH, only if TX2RFEn=1 and TX2Inv=0 LOW Separated from Input Separated from Input Separated from Input Separated from Input Separated from Input Separated from Input Separated from Input Separated from Input High impedance Not changed Pulled to AVDD Not changed HIGH
TX2 NWR NRD NCS D0 to D7 ALE A0 A1 A2 AUX RX VMID RSTPD OSCOUT
7 9 10 11 13 to 20 21 22 23 24 27 29 30 31 32
O I I I I/O I I/O I I O I A I O
Table 10-1: Signal on Pins during Hard Power Down 10.2 Soft Power Down The Soft Power Down-mode is entered immediately by setting bit PowerDown in the Control-Register. All internal current sinks are switched off (including the oscillator buffer). In difference to the Hard Power Down-mode, the digital input-buffers are not separated by the input pads and keep their functionality. The digital output pins do not change their state. After resetting bit PowerDown in the Control-Register it needs 512 clocks until the Soft Power Down mode is left indicated by the PowerDown bit itself. Resetting it does not immediately clear it. It is cleared automatically by the CL RC632 when the Soft Power Down-Mode is left. Note: If the internal oscillator is used, you have to take into account that it is supplied by AVDD and it will take a certain time tosc until the oscillator is stable and the clock cycles can be detected by the internal logic.
93
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
10.3 Stand By Mode
CL RC632
The Stand By-mode is entered immediately by setting bit StandBy in the Control-Register. All internal current sinks are switched off (including the internal digital clock buffer but except the oscillator buffer). Different from the Hard Power Down-Mode, the digital input-buffers are not separated by the input pads and keep their functionality. The digital output pins do not change their state. Different from the Soft Power Down-Mode, the oscillator does not need time to wake up. After resetting bit StandBy in the Control-Register it needs 4 clocks on pin OSCIN until the Stand By-Mode is left indicated by the StandBy bit itself. Resetting it does not immediately clear it. It is cleared automatically by the CL RC632 when the Stand By-Mode is left.
10.4 Receiver Power Down It is power saving to switch off the receiver circuit when it is not needed and switched it on again right before data is to be received from the card. This is done automatically by setting bit RxAutoPD to 1. If it is set to 0 the receiver is continuously switched on.
94
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
11 START UP PHASE
CL RC632
The phases executed during the start up are shown in the following figure.
Start Up Phase tPD tReset tInit
States
Hard Power Down Phase
Reset Phase
Initialising Phase
Ready
Figure 11-1: Start Up Procedure
11.1 Hard Power Down Phase The Hard Power Down Phase is active during the following cases: * Power On Reset caused by power up at pin DVDD (active while DVDD is below the digital reset threshold) * Power On Reset caused by power up at pin AVDD (active while AVDD is below the analog reset threshold) * A HIGH level on pin RSTPD (active while pin RSTPD is HIGH) 11.2 Reset Phase The Reset Phase follows the Hard Power Down Phase automatically. One's the oscillator is running stable, it takes 512 clocks. During the Reset Phase, some of the register bits are pre-set by hardware. The respective reset values are given in the description of each register (see 5.2.). Note: If the internal oscillator is used, you have to take into account that it is supplied by AVDD and that it will take a certain time tosc until the oscillator is stable.
11.3 Initialising Phase The Initialising Phase follows the Reset Phase automatically. It takes 128 clocks. During the Initialising Phase the content of the EPROM blocks 1 and 2 is copied into the registers 10hex to 2Fhex. (see 6.3) Note: At production test, the CL RC632 is initialised with default configuration values. This reduces the -Processors effort for configuring the device to a minimum.
95
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
11.4 Initialising the Parallel Interface-Type
CL RC632
For the different connections for the different -Processor interface types (see 4.3), a certain initialising sequence shall be applied to enable a proper -Processor interface type detection and to synchronise the -Processor's and the CL RC632's Start Up. During the whole Start Up Phase, the Command value reads as 3Fhex. At the end of the Initialising Phase the CL RC632 enters the Idle Command automatically. Consequently the Command value changes to 00hex. To ensure proper detection of the -Processor interface, the following sequence shall be executed: * Read from the Command-Register until the 6 bit register value for Command is 00hex. The internal initialisation phase is now completed and the CL RC632 is ready to be controlled. * Write the value 80hex to the Page-Register to initialise the -Processor interface. * Read the Command-Register. If its value is 00hex the -Processor interface initialisation was successful. Having done the interface initialisation, the linear addressing mode can be activated by writing 0x00 to the page register(s).
96
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
12 OSCILLATOR CIRCUITRY
CL RC632
MF RC531
OSCOUT OSCIN
13.56 MHz 15 pF 15 pF
Figure 12-1: Quartz Connection
The clock applied to the CL RC632 acts as time basis for the coder and decoder of the synchronous system. Therefore stability of the clock frequency is an important factor for proper performance. To obtain highest performance, clock jitter has to be as small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry. If an external clock source is used, the clock signal has to be applied to pin OSCIN. In this case special care for clock duty cycle and clock jitter is needed and the clock quality has to be verified. It needs to be in accordance with the specifications in chapter 22.5.3. Remark: We do not recommend to use an external clock source.
97
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
13 TRANSMITTER PINS TX1 AND TX2
CL RC632
The signal delivered on TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly, using a few passive components for matching and filtering (see chapter 20). For that, the output circuitry is designed with a very low impedance source resistance. The signal of TX1 and TX2 can be controlled via the TxControl Register. 13.1 Configuration of TX1 and TX2 The configuration possibilities of TX1 are described in the table below:
Register Configuration in TxControl TX1RFEn 0 1 FORCE100ASK X 0 Envelope X 0 1 0 1 Signal on TX1 LOW (GND) 13.56 MHz carrier frequency modulated 13.56 MHz carrier frequency LOW 13.56 MHz energy carrier
1
1
Table 13-1: Configurations of Pin TX1 The configuration possibilities of TX2 are described in the table below:
Register Configuration in TxControl TX2RFEn 0 FORCE100 ASK X TX2CW X InvTX2 X 0 0 1 0 0 1 1 1 X 0 1 0 1 0 1 1 1 X X 13.56 MHz carrier frequency, 180 phase shift relative to TX1 LOW 13.56 MHz carrier frequency HIGH 13.56 MHz carrier frequency, 180 phase shift relative to TX1 13.56 MHz carrier frequency 13.56 MHz carrier frequency, 180 phase shift relative to TX1 1 Envelope X 0 1 0 Signal on TX2 LOW 13.56 MHz carrier frequency modulated 13.56 MHz carrier frequency 13.56 MHz carrier frequency modulated, 180 phase shift relative to TX1 13.56 MHz carrier frequency, 180 phase shift relative to TX1 13.56 MHz carrier frequency
X
0 0 1
Table 13-2: Configurations of Pin TX2
98
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
13.2 Operating Distance versus Power Consumption
CL RC632
The user has the possibility to find a trade-off between maximum achievable operating distance and power consumption using different antenna matching circuits by varying the supply voltage at the antenna driver supply pin TVDD. Different antenna matching circuits are described in the Application Note, MIFARE Design of MF RC500 Matching Circuit and Antennas.
13.3 Antenna Driver Output Source Resistance The output source conductance of TX1 and TX2 for driving a HIGH level may be adjusted via the value GsCfgCW in the CwConductance Register in the range from about 1 up to 100 Ohm. The output source conductance of Tx1 and TX2 during the modulation phase may be adjusted via the value GsCfgMod in the ModConductance Register in the same range. The values given are relative to the reference resistance Rsrel, that is measured during production test and stored in the CL RC632 EPROM. It can be obtained from the Product Information Field (see chapter 6.2). The electrical specification can be found in chapter 22.4.3.
99
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
13.3.1 SOURCE RESISTANCE TABLE
GsCfgCW, GsCfgMod [decimal]
0 16 32 48 1 17 2 3 33 18 4 5 19 6 7 49 34 20 8 9 21 10 11 35 22 12 13 23 14 50 36 15
CL RC632
EXPGsCfgCW, EXPGsCfgMod [decimal]
0 1 2 3 0 1 0 0 2 1 0 0 1 0 0 3 2 1 0 0 1 0 0 2 1 0 0 1 0 3 2 0
MANTGsCfgCW, MANTGsCfgMod [decimal]
0 0 0 0 1 1 2 3 1 2 4 5 3 6 7 1 2 4 8 9 5 10 11 3 6 12 13 7 14 2 4 15
Rsrel [Ohm]
1,0000 0,5217 0,5000 0,3333 0,2703 0,2609 0,2500 0,2000 0,1739 0,1667 0,1429 0,1402 0,1351 0,1304 0,1250 0,1111 0,1043 0,1000 0,0909 0,0901 0,0870 0,0833 0,0769 0,0745 0,0714 0,0701 0,0676 0,0667
GsCfgCW, GsCfgMod [decimal]
24 25 37 26 27 51 38 28 29 39 30 52 31 40 41 53 42 43 54 44 45 55 46 47 56 57 58 59 60 61 62 63
EXPGsCfgCW, EXPGsCfgMod [decimal]
1 1 2 1 1 3 2 1 1 2 1 3 1 2 2 3 2 2 3 2 2 3 2 2 3 3 3 3 3 3 3 3
MANTGsCfgCW MANTGsCfgMod [decimal]
8 9 5 10 11 3 6 12 13 7 14 4 15 8 9 5 10 11 6 12 13 7 14 15 8 9 10 11 12 13 14 15
Rsrel [Ohm]
0,0652 0,0580 0,0541 0,0522 0,0474 0,0467 0,0450 0,0435 0,0401 0,0386 0,0373 0,0350 0,0348 0,0338 0,0300 0,0280 0,0270 0,0246 0,0234 0,0225 0,0208 0,0200 0,0193 0,0180 0,0175 0,0156 0,0140 0,0127 0,0117 0,0108 0,0100 0,0093
Table 13-3: Source Resistance of n-Channel Driver Transistor of TX1 and TX2 vs. GsConfCW or GsCfgMod
100
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
13.3.2 FORMULA FOR THE SOURCE RESISTANCE The relative resistance Rsrel can be calculated by
CL RC632
Rsrel =
1
MANTGsCfgCW ( 77 ) 40
EXPGsCfgCW
The relative resistance Rsrel during the modulation phase can be calculated using GsCfgMod, respectively.
13.3.3 CALCULATING THE EFFECTIVE SOURCE RESISTANCE 13.3.3.1 Wiring Resistance Wiring and bonding add a constant offset to the driver resistance, that is relevant if TX1 and TX2 are switched to low impedance. The additional resistance for TX1 can be set approximately to
Rs wire ,TX 1 500m
13.3.3.2 Effective Resistance The source resistances of the driver transistors RsMaxP found in the Product Information Field (see chapter 6.2) are measured at production test with GsCfgCW set to 01hex. To get the driver resistance for a specific value set in GsCfgMod the following formula may be used:
Rs x = (Rsref ,max, p - Rswire ,TX 1 ) Rsrel + Rswire ,TX 1 .
101
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
13.4 Pulse Width
CL RC632
The envelope carries the information of the data signal that shall be transmitted to the card done by coding the data signal according to the Miller code. Furthermore, each pause of the Miller coded signal again is coded as a pulse of certain length. The width of this pulse can be adjusted by means of the ModWidth Register. The pulse length is calculated by
TPulse = 2
where fc = 13.56MHz.
ModWidth + 1 fC
102
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
14 RECEIVER CIRCUITRY
CL RC632
14.1 General The CL RC632 employs an integrated quadrature-demodulation circuit giving the possibility to detect an ISO 14443 compliant subcarrier signal applied to pin RX. The ISO14443-A sub-carrier signal is defined as a Manchester coded ASK-modulated signal. The ISO14443-B sub-carrier signal is defined as an NRZ-L coded BPSK modulated ISO14443-B sub-carrier signal. The quadrature-demodulator uses two different clocks, Q- and I-clock, with a phase shift of 90 between them. Both resulting sub-carrier signals are amplified, filtered and forwarded to a correlation circuitry. The correlation results are evaluated, digitised and passed to the digital circuitry. For all processing units various adjustments can be made to obtain optimum performance.
14.2 Block Diagram Figure 14-1 shows the block diagram of the receiver circuitry. The receiving process includes several steps. First the quadrature demodulation of the carrier signal of 13.56 MHz is done. To achieve an optimum in performance an automatic clock Q calibration is recommended (see 14.3.1). The demodulated signal is amplified by an adjustable amplifier. A correlation circuit calculates the degree of similarity between the expected and the received signal. The bit phase register allows aligning the position of the correlation intervals with the bit grid of the received signal. In the evaluation and digitizer circuitry the valid bits are detected and the digital results are send to the FIFO register. Several tuning steps in this circuit are possible.
ClockQDelay[4:0]
ClockQCalib
ClockQ180 Gain[1:0]
BitPhase[7:0]
CollLevel[3:0] MinLevel[3:0]
RcvClkSelI
RxWait[7:0]
I to Q Conversion
I-clock Q-clock
clock s_valid
RX
13.56 MHz Demodulator
Correlation Circuitry
Evaluation and Digitizer Circuitry
s_data s_coll s_clock
VRxFollQ VRxFollI
VRxAmpQ VRxAmpI
VCorrNI VCorrDI
VCorrNQ VEvalR VEvalL
VCorrDQ
to TestAna OutSel
Figure 14-1: Block Diagram of Receiver Circuitry
The user may observe the signal on its way through the receiver as shown in the block diagram above. One signal at a time may be routed to pin AUX using the TestAnaSelect-Register as described in 21.3.
103
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
14.3 Putting the Receiver into Operation
CL RC632
In general, the default settings programmed in the Start Up Initialisation File are suitable to use the CL RC632 for data communication with MIFARE cards. However, in some environments specific user settings may achieve better performance.
14.3.1 AUTOMATIC CLOCK-Q CALIBRATION The quadrature demodulation concept of the receiver generates a phase signal I-clock and a 90-shifted quadrature signal Q-clock. To achieve an optimum demodulator performance, the Q- and the I-clock have to have a difference in phase of 90. After the reset phase of the CL RC632, a calibration procedure is done automatically. It is possible to have an automatic calibration done at the ending of each Transceive command. To do so, the ClkQCalib bit has to be configured to a value of 0. Configuring this bit to a constant value of 1 disables all automatic calibrations except the one after the reset sequence. It is also possible to initiate one automatic calibration by software. This is done with a 0 to 1 transition of bit ClkQCalib. The details:
calibration impulse from reset sequence calibration impulse from ending of TRANSEIVE command
a rising edge initiates a clock Q calibration
the ClkQCalib bit
Note: The duration of the automatic clock Q calibration takes 65 oscillator periods which is approx. 4,8s. The value of ClkQDelay is proportional to the phase shift between the Q- and the I-clock. The status flag ClkQ180Deg shows, that the phase shift between the Q- and the I-clock is greater than 180. Notes: * * * The start-up configuration file enables an automatically Q-clock calibration after the reset. While ClkQCalib is 1, no automatic calibration is done. Therefore leaving this bit 1 can be used to permanently disable the automatic calibration. It is possible to write data to ClkQDelay via the -Processor. The aim could be a disabling of the automatic calibration and to pre-set the delay by software. But notice, that configuring the delay value by software requires that bit ClkQCalib has already been set to 1 before and that a time interval of at least 4.8s has elapsed since then. Each delay value must be written with the ClkQCalib bit set to 1. If ClkQCalib is 0 the configured delay value will be overwritten by the next interval automatic calibration.
104
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
14.3.2 AMPLIFIER
CL RC632
The demodulated signal has to be amplified with the variable amplifier to achieve the best performance. The gain of the amplifiers can be adjusted by means of the register bits Gain [1:0]. The following gain factors are selectable:
Register Setting 0 1 2 3 Gain Factor [dB] (Simulation Results) 20 24 31 35
Table 14-1: Gain Factors for the Internal Amplifier
105
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
14.3.3 CORRELATION CIRCUITRY
CL RC632
The correlation circuitry calculates the degree of matching between the received and an expected signal. The output is a measure for the amplitude of the expected signal in the received signal. This is done for both, the Q- and the I-channel. The correlator delivers two outputs for each of the two input channels, resulting in four output signals in total. For optimum performance, the correlation circuitry needs the phase information for the signal coming from the card. This information has to be defined by the -Processor by means of the register BitPhase [7:0]. This value defines the phase relation between the transmitter and receiver clock in multiples of tBitPhase = 1/13.56 MHz.
14.3.4 EVALUATION AND DIGITIZER CIRCUITRY For each bit-half of the Manchester coded signal the correlation results are evaluated. The evaluation and digitizer circuit decides from the signal strengths of both bit-halves, whether the current bit is valid, and, if it is valid, the value of the bit itself or whether the current bit-interval contains a collision. To do this in an optimum way, the user may select the following levels: * * MinLevel: Defines the minimum signal strength of the stronger bit-half's signal for being considered valid. CollLevel: Defines the minimum signal strength that has to be exceeded by the weaker half-bit of the Manchester-coded signal to generate a bit-collision. If the signal's strength is below this value, a 1 and 0 can be determined unequivocally. CollLevel defines the minimum signal strength relative to the amplitude of the stronger half-bit.
After transmission of data, the card is not allowed to send its response before a certain time period, called frame guard time in the standard ISO14443. The length of this time period after transmission shall be set in the RxWait-Register. The RxWait-Register defines when the receiver is switched on after data transmission to the card in multiples of one bit-duration. If register bit RcvClkSelI is set to 1, the I-clock is used to clock the correlator and evaluation circuits. If set to 0, the Q-clock is used. Note: It is recommended to use the Q-clock.
106
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
15 SERIAL SIGNAL SWITCH
CL RC632
15.1 General Two main blocks are implemented in the CL RC632. A digital circuitry, comprising state machines, coder and decoder logic and so on and an analog circuitry with the modulator and antenna drivers, receiver and amplification circuitry. The interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins MFIN and MFOUT. This topology supports, that the analog part of the one CL RC632 may be connected to the digital part of another device. The serial signal switch can be used to measure MIFARE(R) and ISO14443 as well I*CODE1 and ISO15693 related signals. Note: The MFIN pin can only be accessed by 106 kbaud according to ISO14443A . The Manchester with Subcarrier- and the Manchester signal can only be accessed at the MFOUT pin at 106 kbaud according to ISO14443A. 15.2 Block Diagram Figure 15-1 describes the serial signal switches. Three different switches are implemented in the serial signal switch in order to use the CL RC632 in different configurations. The serial signal switch may also be used during the design In phase or for test purposes to check the transmitted and received data. Chapter 21.2 describes analog test signals as well as measurements at the serial signal switch. Note: The SL RC400 uses the name SIGOUT for the MFOUT pin. The CLRC 632 functionality includes the
0
0 1 2 3 2 Tx1 Tx2
Serial Data Out
Miller Coder 1 out of 256, RZ or 1 out of 4
1 Envelope MfIn
Modulator
Driver
(Part of) Serial Data Processing
0
Modulator Source
(Part of) Analog Circuitry
0 Manchester Out Manchester with Subcarrier
Serial Data In
Manchester Decoder
1 Internal 2 Manchester with SubCarrier 3 Manchester Transmitt NRZ 2 Envelope Decoder Source
Subcarrier Demodulator
Carrier Demodulator
Rx
Subcarrier Demodulator
0 0 1 1
Manchester
RFU 6
2
3
4
5
7
RFU
0
1
Serial Signal Switch
MfIn MfOut
SignalTo MfOut
Figure 15-1: Serial Signal Switch
107
MfOut Select Digital Test Signal
3
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
test possibilities for the SL RC 400 using the pin MFOUT.
CL RC632
The following chapters describe the relevant registers used to configure and control the serial signal switch. 15.3 Registers Relevant for the Serial Signal Switch The flags DecoderSource define the input signal for the internal Manchester decoder in the following way:
DecoderSource 0 1 2 3 Constant 0 Output of the analog part. This is the default configuration. Direct connection to MFIN, expecting an 847.5 kHz sub-carrier signal modulated by a Manchester coded signal. Direct connection to MFIN, expecting a Manchester coded signal. Input Signal for Decoder
Table 15-1: Values for DecoderSource
ModulatorSource defines the signal that modulates the transmitted 13.56 MHz energy carrier. The modulated signal drives the pins TX1 and TX2.
ModulatorSource 0 1 2 3 Input Signal for Modulator Constant 0 (energy carrier off at pin TX1 and TX2). Constant 1 (continuous energy carrier delivered at pin TX1 and TX2). Modulation signal (envelope) from the internal coder. This is the default configuration. Direct connection to MFIN, expecting a Miller pulse coded signal.
Table 15-2: Values for ModulatorSource
MFOUTSelect selects the output signal, which is routed to the pin MFOUT.
MFOUTSelect 0 1 2 3 4 5 6 7 Constant Low Constant High Modulation signal (envelope) from the internal coder. Serial data stream that is to be transmitted (same as for MFOUTSelect = 2, but not coded by the selected pulse coder yet). Output signal of the receiver circuit (card modulation signal regenerated and delayed) Output signal of the subcarrier demodulator (Manchester-coded card signal) RFU RFU Signal Routed to Pin MFOUT
able 15-3: Values for MFOUTSelect To use MFOUTSelect, the value of test signal control bit SignalToMFOUT has to be 0.
108
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
MIFARE(R) : Usage of the MFIN and MFOUT 15.3.1 ACTIVE ANTENNA CONCEPT
CL RC632
The CL RC632 analog circuitry may be used via the pins MFIN and MFOUT. To do so, the following register settings have to be made:
Register ModulatorSource MFOUTSelect DecoderSource Value 3 4 X Signal Miller Pulse Coded Manchester Coded with sub-carrier At CL RC632 Pin MFIN MFOUT -
Table 15-4: Register setting to use the CL RC632 analog circuitry only
On the other hand, the CL RC632 digital circuitry may be used via the pins MFIN and MFOUT. To do so, the following register settings have to be made:
Register ModulatorSource MFOUTSelect DecoderSource Value X 2 2 Signal Miller Pulse Coded Manchester Coded with sub-carrier At CL RC632 Pin MFOUT MFIN
Table 15-5: Register setting to use the CL RC632 digital circuitry only
Two CL RC632 devices configured in the above described way may be connected to each other via the pins MFOUT and MFIN. Note: The usage of the active antenna concept is only possible with a baudrate of 106kbaud according to ISO14443A.
15.3.2 DRIVING TWO RF-PARTS It is possible, to connect a `passive antenna' to pins TX1, TX2 and RX (via the appropriate filter and matching circuit) and at the same time an Active Antenna to the pins MFOUT and MFIN. In this configuration, two RF-parts may be driven (one after another) by one -Processor.
109
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
16 MIFARE(R) HIGHER BAUDRATES
CL RC632
The MIFARE(R) Classic system is specified with a fix Baud-rate of 106 kBaud for the communication on the RF interface. ISO 14443 in the existing version also defines 106 kBaud at least for the initial phase of a communication between PICC and PCD. To speed up the communication between a terminal and a card to cover requirements for large data transmission the CL RC632 supports the MIFARE(R) higher baudrates communication in combination with e.g. a Controller IC like the MIFARE(R) ProX.
Communication direction CL RC632 based PCD C PICC supporting higher baudrates CL RC632 based PCD Baudrates [kbaud] 106, 212, 424 106, 212, 424
C PICC supporting higher baudrates
Table 16-1 MIFARE(R) Higher Baudrates The MIFARE(R) Higher Baudrates' concept will be described in the Application Note: `MIFARE(R) Implementation of Higher Baudrates'. This Application Note will cover also the integration a MIFARE(R) Higher Baudrates communication concept in current applications.
110
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
17 ISO14443 B
CL RC632
The international standard ISO14443 standard covers 2 communication schemes: the ISO14443-A and the ISO14443-B. The CL RC632 reader IC fully supports the ISO14443. The following registers and flags cover the ISO 14443B communication scheme:
Flags CharSpacing CoderRate EOFWidth FilterAmpDet Force100ASK GSCfgCW GSCfgMod MinLevel NoTxEOF NoTxSOF NoRxEGT NoRxEOF NoRxSOF RxCoding RxFraming SOFWidth SubCPulses TauB TauD TxCoding
Register TypeBFraming CoderControl TypeBFraming BPSKDemControl TxControl CWConductance ModConductance RxTreshhold TypeBFraming TypeBFraming BPSKDemControl BPSKDemControl BPSKDemControl DecoderControl DecoderControl TypeBFraming RxControl1 BPSKDemControl BPSKDemControl CoderControl
Address 0x17, bits 4-3 0x14, bits 5-3 0x17, bit 5 0x1D, bit 4 0x11, bit 4 0x12, bits 5-0 0x13, bits 5-0 0x1C, bits 7-4 0x17, bit 6 0x17, bit 7 0x1D, bit 6 0x1D, bit 5 0x1D, bit 7 0x1A,bit 0 0x1A,bits 4-3 0x17,bits 1-0 0x19, bits 7-5 0x1D, bits 1-0 0x1D, bits 3-2 0x14, bits 2-0
Table 17-1 Registers associated with ISO14443-B
As a reference documentation the international standard ISO14443 `Identification cards- Contactless integrated circuit(s) cards- Proximity cards, part 1-4' can be taken.
Note: Philips Semiconductors does not offer a basic function library to design in the ISO14443 B protocol.
111
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18 CL RC632 COMMAND SET
CL RC632
18.1 General Description The CL RC632 behaviour is determined by an internal state machine capable to perform a certain set of commands. The commands can be started by writing the according command-code to the CommandRegister. Arguments and/or data necessary to process a command are mainly exchanged via the FIFO buffer.
18.2 General Behaviour * * * * Each command, that needs a data stream (or data byte stream) as input will immediately process the data it finds in the FIFO buffer. Each command that needs a certain number of arguments will start processing only when it has received the correct number of arguments via the FIFO buffer. The FIFO buffer is not cleared automatically at command start. Therefore, it is also possible to write the command arguments and/or the data bytes into the FIFO buffer and start the command afterwards. Each command (except the StartUp-Command) may be interrupted by the -Processor by writing a new command code into the Command-Register e.g.: the Idle-Command.
18.3 CL RC632 Commands Overview
Command Code Action Runs the Reset- and Initialisation Phase. StartUp 3Fhex Note: This command can not be activated by software, but only by a Power-On or Hard Reset No action; cancels current command execution. Transmits data from the FIFO buffer to the card. Activates receiver circuitry. Note: Before the receiver actually starts, the state machine waits until the time configured in the register RxWait has passed. Note: This command may be used for test purposes only, since there is no timing relation to the TransmitCommand. 18.3.2 Arguments and Data passed via FIFO Returned Data via FIFO see Chapter
Idle Transmit
00hex 1Ahex
Data Stream
-
18.3.3 18.4.1
Receive
16hex
-
Data Stream
18.4.2
112
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CL RC632 Commands Overview Continued
Command Code Action Transmits data from FIFO buffer to the card and activates automatically the receiver after transmission. Transceive 1Ehex Note: Before the receiver actually starts, the CL RC632 waits until the time configured in the register RxWait has passed. Note: This command is the combination of Transmit and Receive WriteE2 01hex Gets data from FIFO buffer and writes it to the internal EPROM. Reads data from the internal EPROM and puts it into the FIFO buffer. Note: Keys cannot be read back LoadKeyE2 0Bhex Copies a key from the EPROM into the key buffer. Note: related to MIFARE(R) Classic Security Reads a key from the FIFO buffer and puts it into the key buffer. LoadKey 19hex Note: The key has to be prepared in a specific format (refer to 6.4.1, key format) Note: related to MIFARE(R) Classic Security Performs the first part of the Crypto1 card authentication. Note: related to MIFARE(R) Classic Security Performs the second part of the card authentication using the Crypto1 algorithm. Note: related to MIFARE(R) Classic Security LoadConfig 07hex Reads data from EPROM and initialises the CL RC632 registers. Activates the CRC-Coprocessor. CalcCRC 12hex Note: The result of the CRC calculation can be read from the registers CRCResultLSB and CRCResultMSB Data Byte-Stream Start Address LSB Start Address MSB Start Address LSB Start Address MSB Data Byte Stream Start Address LSB Start Address MSB Number of Data Bytes Start Address LSB Start Address MSB Data Stream Arguments and Data passed via FIFO
CL RC632
Returned Data via FIFO
see Chapter
Data Stream
18.4.3
-
18.6.1
ReadE2
03hex
Data Bytes
18.6.2
-
18.9.1
Byte0 (LSB) Byte1 ... Byte 10 Byte11 (MSB)
-
18.9.2
Authent1
0Chex
Card's Auth-Command Card's Block Address Card's Serial Number LSB Card's Serial Number Byte1 Card's Serial Number Byte2 Card's Serial Number MSB
-
18.9.3
Authent2
14hex
-
-
18.9.4
-
18.7.1
-
18.7.2
Table 18-1: CL RC632 Command Overview
113
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.3.1 BASIC STATES 18.3.2 STARTUP COMMAND 3FHEX
Command Codehex Action Runs the Reset- and Initialisation Phase StartUp 3F Note: This command can not be activated by software, but only by a Power-On or Hard Reset Arguments and Data
CL RC632
Returned Data
-
The StartUp-Command runs the Reset- and Initialisation Phase. It does not need or return any data. It can not be activated by the -Processor but is started automatically after one of the following events: * Power On Reset caused by power up at Pin DVDD * Power On Reset caused by power up at Pin AVDD * Negative Edge at Pin RSTPD The Reset-Phase defines certain register bits by an asynchronous reset. The Initialisation-Phase defines certain registers with values taken from the EPROM. When the StartUp-Command has finished, the Idle-Command is entered automatically. Notes: * The -Processor must not write to the CL RC632 as long as the CL RC632 is busy executing the StartUp-Command. To ensure this, the -Processor shall poll for the Idle-Command to determine the end of the Initialisation Phase (see also chapter 11.4). As long as the StartUp-Command is active, only reading from page 0 of the CL RC632 is possible. The StartUp-Command can not be interrupted by the -Processor.
* *
18.3.3 IDLE COMMAND 00HEX
Command Idle Codehex 00 Action No action, cancels current command execution Arguments and Data Returned Data -
The Idle-Command switches the CL RC632 to its inactive state. In this Idle-state it waits for the next command. It does not need or return any data. The device automatically enters the Idle-state when a command finishes. In this case the CL RC632 simultaneously initiates an interrupt request by setting bit IdleIRq. Triggered by the -Processor, the Idle-Command may be used to stop execution of all other commands (except the StartUp Command). In that case no IdleIRq is generated. Remark: Stopping a command with the Idle Command does not clear the FIFO buffer content.
114
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.4 Commands for ISO14443 A Card Communication
CL RC632
The CL RC632 is a fully ISO 14443 and ISO15693 and I*CODE1 compliant reader IC. Therefore, the command set of this IC allows more flexibility and more generalised commands compared to MIFARE or I*CODE1 dedicated reader ICs. The following chapter describes the command set for card communication for ISO14443 A related communication schemes. 18.4.1 TRANSMIT COMMAND 1AHEX
Command Transmit Codehex 1A Action Transmits data from FIFO buffer to the card Arguments and Data Data Stream Returned Data -
The Transmit-Command takes data from the FIFO buffer and forwards it to the transmitter. It does not return any data. The Transmit-Command can only be started by the -Processor.
18.4.1.1 Working with the Transmit Command To transmit data one of the following sequences may be used: 1. All data, that shall be transmitted to the card is written to the FIFO while the Idle-Command is active. After that, the command code for the Transmit-Command is written to the Command-Register. Note: This is possible for transmission of data with a length of up to 64 bytes. 2. The command code for the Transmit-Command is written to the Command-Register first. Since no data is available in the FIFO, the command is only enabled but transmission is not triggered yet. Data transmission really starts with the first data byte written to the FIFO. To generate a continuous data stream on the RF-interface, the -Processor has to put the next data bytes to the FIFO in time. Note: This allows transmission of data of any length but requires that data is available in the FIFO in time. 3. A part of the data, that shall be transmitted to the card is written to the FIFO while the Idle-Command is active. After that, the command code for the Transmit-Command is written to the Command-Register. While the Transmit-Command is active, the -Processor may feed further data to the FIFO, causing the transmitter to append it to the transmitted data stream. Note: This enables transmission of data of any length but requires that data is available in the FIFO in time. When the transmitter requests the next data byte to keep the data stream on the RF-interface continuous but the FIFO buffer is empty, the Transmit-Command automatically terminates. This causes the internal state machine to change its state from Transmit to Idle. If data transmission to the card is finished, the CL RC632 sets the flag TxIRq to signal it to the -Processor. Remark: If the -Processor overwrites the transmit code in the Command-Register with the Idle-Command or any other command, transmission stops immediately with the next clock cycle. This may produce output signals that are not according to ISO14443-A.
18.4.1.2 RF-Channel Redundancy and Framing Each transmitted ISO14443 frame consists of a SOF (start of frame) pattern, followed by the data stream and is closed by an EOF (end of frame) pattern. These different phases of the transmit sequence may be monitored by watching ModemState of PrimaryStatus-Register (see 18.4.4).
115
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CL RC632
Depending on the setting of bit TxCRCEn in the ChannelRedundancy-Register a CRC is calculated and appended to the data stream. The CRC is calculated according the settings in the ChannelRedundancy Register. Parity generation is handled according the settings in the ChannelRedundancy-Register (bits ParityEn and ParityOdd). 18.4.1.3 Transmission of Bit Oriented Frames The transmitter may be configured to send an incomplete last byte. To achieve this TxLastBits has to be set to a value unequal zero. This is shown in the figure below.
TxLastBits = 0
SOF
Bit0
Bit7
P
Bit0
Bit7
P
EOF
TxLastBits = 7
SOF
Bit0
Bit7
P
Bit0
Bit6
EOF
TxLastBits = 1
SOF
Bit0
Bit7
P
Bit0
EOF
Figure 18-1: Transmitting Bit Oriented Frames
The figure shows the data stream if ParityEn is set in ChannelRedundancy-Register. All fully transmitted bytes are followed by a parity check bit, but the incomplete byte is not followed by a parity check bit. After transmission, TxLastBits is cleared automatically. Note: If TxLastBits is not equal to zero CRC generation has to be disabled. This is done by clearing the bit TxCRCEn in the ChannelRedundancy Register.
116
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.4.1.4 Transmission of Frames with more than 64 Bytes
CL RC632
To generate frames with more than 64 bytes, the -Processor has to write data into the FIFO buffer while the Transmit Command is active. The state machine checks the FIFO status when it starts transmitting the last bit of the actual data stream (the check time is marked below with arrows).
TxLastBits FIFO Length FIFO empty TxData Check FIFO empty Accept Further Data
TxLastBits = 0
0x01
0x00
Bit7 Bit0
Bit7 Bit0
Bit7
Figure 18-2: Timing for Transmitting Byte Oriented Frames
As long as the internal signal `Accept Further Data' is 1 further data may be loaded to the FIFO. The CL RC632 appends this data to the data stream transmitted via the RF-interface. If the internal signal `Accept Further Data' is 0 the transmission will terminate. All data written into the FIFO buffer after `Accept Further Data' went 0 will not be transmitted anymore, but remain in the FIFO buffer. Remark: If parity generation is enabled (ParityEn bit is 1) the parity bit is the last bit to be transmitted. This delays the signal `Accept Further Data' for one bit duration.
117
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
CL RC632
If TxLastBits is unequal zero the last byte is not transmitted completely, but only the number of bits set in TxLastBits are transmitted (starting with the least significant bit). Thus, the internal state machine has to check the FIFO status at an earlier point in time (shown in the figure below).
N_WR (FIFO Data) TxLastBits FIFO Length FIFO empty TxData Check FIFO empty Accept Further Data
TxLastBits = 4
0x01
0x00
0x01
0x00
Bit4
Bit7 Bit0
Bit3 Bit4
Bit7 Bit0
Bit3
Figure 18-3: Timing for Transmitting Bit Oriented Frames
Since TxLastBits = 4 in this example, transmission stops after Bit 3 is transmitted. If configured, the frame is completed with an EOF. The figure above also shows a write access to the FIFOData Register right before the FIFO's status is checked. This leads to `FIFO empty' going to 0 again and therefore `Accept Further Data' stays active. The new byte written is transmitted via the RF-interface. `Accept Further Data' is changed only by the `Check FIFO empty' function. This function verifies `FIFO empty' one bit duration before the last expected bit transmission.
Frame Definition 8 Bit with Parity 8 Bit without Parity x Bit without Parity
Verification at: 8th Bit 7th Bit (x-1)th Bit
118
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.4.2 RECEIVE COMMAND 16HEX
Command Receive Codehex 16 Action Activates Receiver Circuitry Arguments and Data -
CL RC632
Returned Data Data Stream
The Receive-Command activates the receiver circuitry. All data received from the RF interface is returned via the FIFO buffer. The Receive-Command can be started either by the -Processor or automatically during execution of the Transceive-Command. Note: This command may be used for test purposes only, since there is no timing relation to the TransmitCommand. 18.4.2.1 Working with the Receive Command After starting the Receive Command the internal state machine decrements the value set in the RxWaitRegister with every bit-clock. From 3 down to 1 the analog receiver circuitry is prepared and activated. When the counter reaches 0, the receiver starts monitoring the incoming signal at the RF-interface. If the signal strength reaches a level higher than the value set in the MinLevel-Register it finally starts decoding. The decoder stops, if no more signal can be detected on the receiver input pin Rx. The decoder indicates termination of operation by setting bit RxIRq. The different phases of the receive sequence may be monitored by watching ModemState of the PrimaryStatus-Register (see 18.4.4). Note: Since the counter values from 3 to 0 are necessary to initialise the analog receiver circuitry the minimum value for RxWait is 3.
18.4.2.2 RF-Channel Redundancy and Framing The decoder expects a SOF pattern at the beginning of each data stream. If a SOF is detected, it activates the serial to parallel converter and gathers the incoming data bits. Every completed byte is forwarded to the FIFO. If an EOF pattern is detected or the signal strength falls below MinLevel set in the RxThreshold Register, the receiver and the decoder stop, the Idle-Command is entered and an appropriate response for the -Processor is generated (interrupt request activated, status flags set). If bit RxCRCEn in the ChannelRedundancy Register is set a CRC block is expected. The CRC block may be one byte or two bytes according to bit CRC8 in the ChannelRedundancy Register. Remark: The received CRC block is not forwarded to the FIFO buffer if it is correct. This is realised by shifting the incoming data bytes through an internal buffer of either one or two bytes (depending on the defined CRC). The CRC block remains in this internal buffer. As a consequence all data bytes are available in the FIFO buffer one or two bytes delayed. If the CRC fails all received bytes are forwarded to the FIFO buffer (including the faulty CRC itself). If ParityEn is set in the ChannelRedundancy Register a parity bit is expected after each byte. If bit ParityOdd is set to 1, the expected parity is an odd parity, otherwise an even parity is expected.
119
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.4.2.3 Collision Detection
CL RC632
If more than one card is within the RF-field during the card selection phase, they will respond simultaneously. The CL RC632 supports the algorithm defined in ISO14443-A to resolve data-collisions of cards serial numbers by doing the so-called anti-collision procedure. The basis for this is the ability to detect bitcollisions. Bit-collision detection is supported by the used bit-coding scheme, namely the Manchester-coding. If in the first and second half-bit of a bit a sub-carrier modulation is detected, instead of forwarding a 1 or a 0 a bit collision will be signalled. To distinguish a 1 or 0-bit from a bit-collision, the CL RC632 uses the setting of CollLevel. If the amplitude of the half-bit with smaller amplitude is larger than defined by CollLevel, the CL RC632 indicates a bit-collision. If a bit-collision is detected, the error flag CollErr is set. If a bit-collision is detected in a parity bit, the flag ParityErr is set indicating a parity error. Independent from the detected collision the receiver continues receiving the incoming data stream. In case of a bit-collision, the decoder forwards 1 at the collision position. Note: As an exception, if bit ZeroAfterColl is set, all bits received after the first bit-collision are forced to zero, regardless whether a bit-collision or an unequivocal state has been detected. This feature eases for the software to carry out the anti-collision procedure defined in ISO14443-A. When the first bit collision in a frame is detected, the bit position of this collision is stored in the CollPos Register. The collision position follows the table below:
Collision in Bit SOF LSBit of LSByte ... MSBit of LSByte LSBit of second Byte ... MSBit of second Byte LSBit of third Byte ... Value of CollPos 0 1 ... 8 9 ... 16 17 ...
Table 18-2: Returned Values for Bit Collision Positions The parity bits are not counted in CollPos, since a bit-collision in a parity bit per definition succeeds a bitcollision in the data bits. If a collision is detected in the SOF a frame error is reported and no data is forwarded to the FIFO buffer. In this case the receiver continues to monitor the incoming signal and generates the correct notifications to the -Processor when the ending of the faulty input stream is detected. This helps the -Processor to determine the time when it is allowed next to send anything to the card.
120
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.4.2.4 Receiving Bit Oriented Frames
CL RC632
The receiver can handle byte streams with incomplete bytes, resulting in bit oriented frames. To support this, the following values may be used: * RxAlign selects a bit offset for the first incoming byte, e.g. if RxAlign is set to 3, the first 5 bits received are forwarded to the FIFO buffer. Further bits are packed into bytes and forwarded. After reception, RxAlign is cleared automatically. If RxAlign is set to zero, all incoming bits are packed into one byte. RxLastBits returns the number of bits valid in the last received byte, e.g. if RxLastBits evaluates to 5 at the end of the receiving command, the 5 least significant bits are valid. RxlastBits evaluates to zero if the last byte is complete.
*
RxLastBits is valid only, if no frame error is indicated by the flag FrameErr. If RxAlign is set to a value other than zero and also ParityEn is active, the first parity bit is not checked but ignored.
18.4.2.5 Communication Errors The following table shows which event causes the setting of error flags:
Cause Received data did not start with a SOF pattern. The CRC block is not equal the expected value. The received data is shorter than the CRC block. The parity bit is not equal the expected value (e. g. a bit collision occurs when a parity is expected) A collision is detected. Bit, that is set FramingErr CRCErr CRCErr ParErr CollErr
Table 18-3: Communication Error Table
121
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.4.3 TRANSCEIVE COMMAND 1EHEX
Command Transceive Codehex 1E Action Arguments and Data
CL RC632
Returned Data Data Stream
Transmits data from FIFO buffer to the card and Data Stream then activates automatically the receiver
The Transceive-Command first executes the Transmit-Command (see 18.4.1) and then automatically starts the Receive-Command (see 18.4.2). All data that shall be transmitted is forwarded via the FIFO buffer and all data received is returned via the FIFO buffer. The Transceive-Command can be started only by the -Processor. Note: To adjust the timing relation between transmitting and receiving, the RxWait Register is used to define the time delay from the last bit transmitted until the receiver is activated. Furthermore, the BitPhase Register determines the phase-shift between the transmitter and the receiver clock. 18.4.4 STATES OF THE CARD COMMUNICATION The actual state of the transmitter and receiver state machine can be fetched from ModemState in the PrimaryStatus Register. The assignment of ModemState to the internal action is shown in the following table:
ModemState 000 001 010 011 100 101 110 111 Name of State Idle TxSOF TxData TxEOF GoToRx1 GoToRx2 PrepareRx AwaitingRx Receiving Description Neither the transmitter nor the receiver is in operation, since none of them is started or the transmitter has not got input data Transmitting the `Start Of Frame' Pattern Transmitting data from the FIFO buffer (or redundancy check bits) Transmitting the `End Of Frame' Pattern Intermediate state passed, when receiver starts Intermediate state passed, when receiver finishes Waiting until the time period selected in the RxWait Register has expired Receiver activated; Awaiting an input signal at pin Rx Receiving data
Table 18-4: Meaning of ModemState
122
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.4.5 STATE DIAGRAM FOR THE CARD COMMUNICATION
CL RC632
Command = (Transmit OR Receive OR Transceive)
Idle (000)
FI C FO (T omm no t ra ns an em m d = pty it AN OR D Tr an sc ei ve )
Co m Re ma ce nd i ve =
TxSOF (001)
GoToRx1 (100)
next bit clock SOF transmitted
TxData (010)
PrepareRx (101)
Data transmitted
RxWaitCounter =0
RxMultiple = 1
TxEOF (011)
AwaitingRx (110)
Signal Strength > MinLevel EOF transmitted AND Command = Transceive
Receiving (111)
EOF transmitted AND Command = Transmit
Frame Received
End of Receive frame AND RxMultiple = 0
GoToRx2 (100)
Set CommandRegister = Idle (000)
Figure 18-4: State Diagram: Card Communication
123
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.5 Commands for I*CODE1 and ISO15693 Label Communication
CL RC632
The CL RC632 is a fully ISO 14443 and ISO15693 and I*CODE1 compliant reader IC. Therefore, the command set of this IC allows more flexibility and more generalised commands compared to MIFARE or I*CODE1 dedicated reader ICs. The following chapter describes the command set for card communication for I*CODE1 and ISO15693 related communication schemes in general.
18.5.1 TRANSMIT COMMAND 1AHEX
Command Transmit Codehex 1A Action Transmits data from FIFO buffer to the label Arguments and Data Data Stream Returned Data -
The Transmit-Command takes data from the FIFO buffer and forwards it to the transmitter. It does not return any data. The Transmit-Command can only be started by the -Processor. 18.5.1.1 Working with the Transmit Command To transmit data one of the following sequences may be used: 1. All data, that shall be transmitted to the label is written to the FIFO while the Idle-Command is active. After that, the command code for the Transmit-Command is written to the Command-Register. Note: This is possible for transmission of data with a length of up to 64 bytes. 2. The command code for the Transmit-Command is written to Command-Register first. Since no data is available in the FIFO, the command is only enabled but transmission is not triggered yet. Data transmission really starts with the first data byte written to the FIFO. To generate a continuous data stream on the RF-interface, the -Processor has to put the next data bytes to the FIFO in time. Note: This allows transmission of data of any length but requires that data is available in the FIFO in time. 3. A part of the data, that shall be transmit to the label is written to the FIFO while the Idle-Command is active. After that, the command code for the Transmit-Command is written to the Command-Register. While the Transmit-Command is active, the -Processor may feed further data to the FIFO, causing the transmitter to append it to the transmitted data stream. Note: This enables transmission of data of any length but requires that data is available in the FIFO in time. When the transmitter requests the next data byte to keep the data stream on the RF-interface continuous but the FIFO buffer is empty, the Transmit-Command automatically terminates. This causes the internal state machine to change its state from Transmit to Idle. If data transmission to the label is finished, the CL RC632 sets the flag TxIRq to signal it to the -Processor. Remark: If the -Processor overwrites the transmit code in the Command-Register with the Idle-Command or any other command, transmission stops immediately with the next clock cycle. This may produce output signals that are not according to the standard ISO 15693 or the I*CODE1 protocol.
124
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.5.1.2 RF-Channel Redundancy and Framing
CL RC632
Each transmitted ISO 15693 frame consists of a SOF (start of frame) pattern, followed by the data stream and is closed by an EOF (end of frame) pattern. All I*CODE1 command frames consists of a START PULSE followed by the data stream. The I*CODE1 commands have a fix length and no EOF is needed. These different phases of the transmit sequence may be monitored by watching ModemState of PrimaryStatusRegister (see 18.4.4). Depending on the setting of bit TxCRCEn in the ChannelRedundancy-Register a CRC is calculated and appended to the data stream. The CRC is calculated according the settings in the ChannelRedundancy Register. 18.5.1.3 Transmission of Frames with more than 64 Bytes To generate frames with more than 64 bytes, the -Processor has to write data into the FIFO buffer while the Transmit Command is active. The state machine checks the FIFO status when it starts transmitting the last bit of the actual data stream (the check time is marked below with arrows).
TxLastBits FIFO Length FIFO empty TxData Check FIFO empty Accept Further Data
TxLastBits = 0
0x01
0x00
Bit7 Bit0
Bit7 Bit0
Bit7
Figure 18-5: Timing for Transmitting Byte Oriented Frames
As long as the internal signal `Accept Further Data' is 1 further data may be loaded into the FIFO. The CL RC632 appends this data to the data stream transmitted via the RF-interface. If the internal signal `Accept Further Data' is 0 the transmission will terminate. All data written into the FIFO buffer after `Accept Further Data' went 0 will not be transmitted anymore, but remain in the FIFO buffer.
125
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.5.2 RECEIVE COMMAND 16HEX
Command Receive Codehex 16 Action Activates Receiver Circuitry Arguments and Data -
CL RC632
Returned Data Data Stream
The Receive-Command activates the receiver circuitry. All data received from the RF interface is returned via the FIFO buffer. The Receive-Command can be started either by the -Processor or automatically during execution of the Transceive-Command. Note: This command may be used for test purposes only, since there is no timing relation to the TransmitCommand. 18.5.2.1 Working with the Receive Command After starting the Receive Command the internal state machine decrements the value set in the RxWaitRegister with every bit-clock. From 3 down to 1 the analog receiver circuitry is prepared and activated. When the counter reaches 0, the receiver starts monitoring the incoming signal at the RF-interface. If the signal strength reaches a level higher than the value set in the MinLevel-Register it finally starts decoding. The decoder stops, if no more signal can be detected on the receiver input pin Rx. The decoder indicates termination of operation by setting bit RxIRq. The different phases of the receive sequence may be monitored by watching ModemState of the PrimaryStatus-Register (see 18.4.4). Note: Since the counter values from 3 to 0 are necessary to initialise the analog receiver circuitry the minimum value for RxWait is 3.
18.5.2.2 RF-Channel Redundancy and Framing For ISO 15693 the decoder expects a SOF pattern at the beginning of each data stream. If a SOF is detected, it activates the serial to parallel converter and gathers the incoming data bits. For I*CODE1 the decoder do not expects a SOF pattern at the beginning of each data stream. It activates the serial to parallel converter with the first received bit of the data. Every completed byte is forwarded to the FIFO. If an EOF pattern (ISO15693) is detected or the signal strength falls below MinLevel set in the RxThreshold Register, the receiver and the decoder stop, the Idle-Command is entered and an appropriate response for the Processor is generated (interrupt request activated, status flags set). If bit RxCRCEn in the ChannelRedundancy Register is set a CRC block is expected. The CRC block may be one byte or two bytes according to bit CRC8 in the ChannelRedundancy Register. Remark: The received CRC block is not forwarded to the FIFO buffer if it is correct. This is realised by shifting the incoming data bytes through an internal buffer of either one or two bytes (depending on the defined CRC). The CRC block remains in this internal buffer. As a consequence all data bytes are available in the FIFO buffer one or two bytes delayed. If the CRC fails all received bytes are forwarded to the FIFO buffer (including the faulty CRC itself).
126
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.5.2.3 Collision Detection
CL RC632
If more than one label is within the RF-field during the label selection phase, they will respond simultaneously. The CL RC632 supports the algorithm defined in ISO 15693 as well as the I*CODE1 anticollision algorithm to resolve data-collisions of label serial numbers by doing the so-called anti-collision procedure. The basis for this is the ability to detect bit-collisions. Bit-collision detection is supported by the used bit-coding scheme, namely the Manchester-coding. If in the first and second half-bit of a bit a sub-carrier modulation is detected, instead of forwarding a 1 or a 0 a bit collision will be signalled. To distinguish a 1 or 0-bit from a bit-collision, the CL RC632 uses the setting of CollLevel. If the amplitude of the half-bit with smaller amplitude is larger than defined by CollLevel, the CL RC632 indicates a bit-collision. If a bit-collision is detected, the error flag CollErr is set. Independent from the detected collision the receiver continues receiving the incoming data stream. In case of a bit-collision, the decoder forwards 1 at the collision position. Note: As an exception, if bit ZeroAfterColl is set, all bits received after the first bit-collision are forced to zero, regardless whether a bit-collision or an unequivocal state has been detected. This feature eases for the software to carry out the anti-collision procedure defined in ISO 15693. When the first bit collision in a frame is detected, the bit position of this collision is stored in the CollPos Register.
The collision position follows the table below:
Collision in Bit SOF LSBit of LSByte ... MSBit of LSByte LSBit of second Byte ... MSBit of second Byte LSBit of third Byte ... Value of CollPos 0 1 ... 8 9 ... 16 17 ...
Table 18-5: Returned Values for Bit Collision Positions
If a collision is detected in the SOF a frame error is reported and no data is forwarded to the FIFO buffer. In this case the receiver continues to monitor the incoming signal and generates the correct notifications to the -Processor when the ending of the faulty input stream is detected. This helps the -Processor to determine the time when it is allowed next to send anything to the label.
127
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.5.2.4 Communication Errors The following table shows which event causes the setting of error flags:
Cause Received data did not start with a SOF pattern. The CRC block is not equal the expected value. The received data is shorter than the CRC block. A collision is detected.
CL RC632
Bit, that is set FramingErr CRCErr CRCErr CollErr
Table 18-6: Communication Error Table
18.5.3 TRANSCEIVE COMMAND 1EHEX
Command Transceive Codehex 1E Action Transmits data from FIFO buffer to the label and then activates automatically the receiver Arguments and Data Data Stream Returned Data Data Stream
The Transceive-Command first executes the Transmit-Command (see 18.4.1) and then automatically starts the Receive-Command (see 18.4.2). All data that shall be transmitted is forwarded via the FIFO buffer and all data received is returned via the FIFO buffer. The Transceive-Command can be started only by the -Processor. Note: To adjust the timing relation between transmitting and receiving, the RxWait Register is used to define the time delay from the last bit transmitted until the receiver is activated. Furthermore, the BitPhase Register determines the phase-shift between the transmitter and the receiver clock. 18.5.4 STATES OF THE LABEL COMMUNICATION The actual state of the transmitter and receiver state machine can be fetched from ModemState in the PrimaryStatus Register. The assignment of ModemState to the internal action is shown in the following table:
ModemState 000 001 010 011 100 101 110 111 Name of State Idle TxSOF TxData TxEOF GoToRx1 GoToRx2 PrepareRx AwaitingRx Receiving Description Neither the transmitter nor the receiver is in operation, since none of them is started or the transmitter has not got input data Transmitting the `Start Of Frame' Pattern Transmitting data from the FIFO buffer (or redundancy check bits) Transmitting the `End Of Frame' Pattern Intermediate state passed, when receiver starts Intermediate state passed, when receiver finishes Waiting until the time period selected in the RxWait Register has expired Receiver activated; Awaiting an input signal at pin Rx Receiving data
Table 18-7: Meaning of ModemState 18.5.5 STATE DIAGRAM FOR THE LABEL COMMUNICATION
128
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
Command = (Transmit OR Receive OR Transceive)
CL RC632
Idle (000)
FI C FO (T omm no t ra ns a n em m d = pty it AN O R D Tr an sc ei ve )
Co m Re ma ce nd iv e =
TxSOF (001)
GoToRx1 (100)
next bit clock SOF transmitted
TxData (010)
PrepareRx (101)
Data transmitted
RxWaitCounter =0
RxMultiple = 1 && TimeSlotPeriod > 0 && TimeSlot Trigger && Data in FIFO
TxEOF (011)
AwaitingRx (110)
Signal Strength > MinLevel EOF transmitted AND Command = Transceive
Receiving (111)
EOF transmitted AND Command = Transmit Frame Received
End of Receive frame && RxMultiple = 0 && TimeSlotPeriod = 0
GoToRx2 (100)
Set CommandRegister = Idle (000)
RxMultiple = 0 && TimeSlotPeriod > 0 && TimeSlot Trigger && Data in FIFO
Idle (000)
Preparing to send the Quit value
Remark: I*CODE1 do not have a SOF and a EOF
129
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.6 Commands to Access the EPROM 18.6.1 WRITEE2 COMMAND 01HEX 18.6.1.1 Overview
Arguments and Data passed via FIFO Start Address LSB Start Address MSB Data Byte Stream
CL RC632
Command
Codehex
Action
Returned Data via FIFO -
WriteE2
01
Get data from FIFO buffer and write it to the EPROM
The WriteE2-Command interprets the first two bytes in the FIFO buffer as EPROM starting byte-address. Any further bytes are interpreted as data bytes and are programmed into the EPROM, starting from the given EPROM starting byte-address. This command does not return any data. The WriteE2-Command can only be started by the -Processor. It will not stop automatically but has to be stopped explicitly by the -Processor by issuing the Idle-Command. 18.6.1.2 Programming Process One byte up to 16 byte can be programmed into the EEPROM in one programming cycle. The time needed will be in any case about 5.8ms. The state machine copies all data bytes prepared in the FIFO buffer to the EPROM input buffer. The internal EPROM input buffer is 16 byte long, which is equal the block size of the EPROM. A programming cycle is started either if the last position of the EPROM input buffer is written or if the last byte of the FIFO buffer has been fetched. As long as there are unprocessed bytes in the FIFO buffer or the EPROM programming cycle still is in progress, the flag E2Ready is 0. If all data from the FIFO buffer are programmed into the EPROM, the flag E2Ready is set to1. Together with the rising edge of E2Ready the interrupt request flag TxIRq indicates a 1. This may be used to generate an interrupt when programming of all data is finished. After the E2Ready bit is set to 1, the WriteE2-Command may be stopped by the -Processor by issuing the Idle-Command. Note: During the E2PROM programming indicated by E2Ready = 0 the WRITEE2 command cannot be stopped by any other command.
130
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.6.1.3 Timing Diagram The following diagram shows programming of 5 bytes into the EPROM:
tprg,del
CL RC632
NWrite Data
WriteE2 command active
Write Adr E2 LSB Adr MSB Byte0 Byte1 Byte2 Byte3 Byte4 Idle Cmd
tprog
tprog
tprog
EPROM Programming E2Ready TxIRq
Programming Byte0
Programming Byte1, Byte2, and Byte3
Programming Byte4
Figure 18-7: Timing Diagram for EPROM programming
Explanation: It is assumed, that the CL RC632 finds and reads Byte 0 before the -Processor is able to write Byte 1 (tprog,del = 300 ns). This causes the CL RC632 to start the programming cycle, which needs about tprog = 5.8 ms. In the meantime the -Processor stores Byte 1 to Byte 4 to the FIFO buffer. Assuming, that the EPROM starting byte-address is e.g. 16Chex then Byte 0 is stored exactly there. The CL RC632 copies the following data bytes into the EPROM input buffer. Copying Byte 3, it detects, that this data byte has to be programmed at the EPROM byte-address 16Fhex. Since this is the end of the memory block, the CL RC632 automatically starts a programming cycle. In the next turn, Byte 4 will be programmed at the EPROM byteaddress 170hex. Since this is the last data byte, the flags (E2Ready and TxIRq) that indicate the end of the EPROM programming activity will be set. Although all data has been programmed into the E2PROM, the CL RC632 stays in the WriteE2-Command. Writing further data to the FIFO would lead to further EPROM programming, continuing at the EPROM byte-address 171hex. The command is stopped using the Idle-Command.
18.6.1.4 Error Flags for the WriteE2 Command Programming is inhibited for the EPROM blocks 0 (EPROM's byte-address 00hex to 0Fhex). Programming to these addresses sets the flag AccessErr. No programming cycle is started. Addresses above 1FFhex are taken modulo 200hex (for the EPROM memory organisation, refer to chapter 6.).
131
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.6.2 READE2 COMMAND 03HEX 18.6.2.1 Overview
Command ReadE2 Codehex 03 Action Reads data from EPROM and puts it to the FIFO buffer Arguments Start Address LSB Start Address MSB Number of Data Bytes
CL RC632
Returned Data Data Bytes
The ReadE2-Command interprets the first two bytes found in the FIFO buffer as EPROM starting byte-address. The next byte specifies the number of data bytes that shall be returned. When all three argument-bytes are available in the FIFO buffer, the specified number of data bytes is copied from the EPROM into the FIFO buffer, starting from the given EPROM starting byte-address. The ReadE2-Command can be triggered only by the -Processor. It stops automatically when all data has been delivered. 18.6.2.2 Error Flags for the ReadE2 Command Reading is inhibited for the EPROM blocks 8hex up to 1Fhex ( key memory area). Reading from these addresses sets the flag AccessErr to 1. Addresses above 1FFhex are taken modulo 200hex (for the EPROM memory organisation, refer to chapter 6).
18.7 Diverse Commands 18.7.1 LOADCONFIG COMMAND 07HEX 18.7.1.1 Overview
Command LoadConfig Codehex 07 Action Reads data from EPROM and initialises the registers Arguments and Data Start Address LSB Start Address MSB Returned Data -
The LoadConfig-Command interprets the first two bytes found in the FIFO buffer as EPROM starting byte-address. When the two argument-bytes are available in the FIFO buffer, 32 bytes from the EPROM are copied into the CL RC632 control and configuration registers, starting at the given EPROM starting byte-address. The LoadConfig-Command can only be started by the -Processor. It stops automatically when all relevant registers have been copied.
132
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.7.1.2 Register Assignment
CL RC632
The 32 bytes of EPROM content, beginning with the EPROM starting byte-address, is written to the CL RC632 register 10hex up to register 2Fhex (for the EPROM memory organisation see also 6). Note: The procedure for the register assignment is the same as it is for the Start Up Initialisation (see 11.3). The difference is, that the EPROM starting byte-address for the Start Up Initialisation is fixed to 10hex (Block 1, Byte 0). With the LoadConfig-Command it can be chosen.
18.7.1.3 Relevant Error Flags for the LoadConfig-Command Valid EPROM starting byte-addresses are in the range from 10hex up to 60hex. Copying from block 8hex up to 1Fhex (keys) is inhibited. Reading from these addresses sets the flag AccessErr to 1. Addresses above 1FFhex are taken modulo 200hex (for the EPROM memory organisation refer to chapter 6).
18.7.2 CALCCRC COMMAND 12HEX 18.7.2.1 Overview
Command CalcCRC Codehex 12 Action Activates the CRC-Coprocessor Arguments and Data Data Byte-Stream Returned Data -
The CalcCRC-Command takes all data from the FIFO buffer as input bytes for the CRC-Coprocessor. All data stored in the FIFO buffer before the command is started will be processed. This command does not return any data via the FIFO buffer, but the content of the CRC-register can be read back via the CRCResultLSB-register and the CRCResultMSB-register. The CalcCRC-Command can only be started by the -Processor. It does not stop automatically but has to be stopped explicitly by the -Processor with the Idle-Command. If the FIFO buffer is empty, the CalcCRC-Command waits for further input from the FIFO buffer.
133
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.7.2.2 CRC-Coprocessor Settings For the CRC-Coprocessor the following parameters may be configured:
Parameter CRC Register Length CRC Algorithm CRC Preset Value Value 8 Bit or 16 Bit CRC Algorithm according ISO14443-A or according ISO/IEC3309 Any Bit CRC8 CRC3309 CRCPresetLSB, CRCPresetMSB
CL RC632
Register ChannelRedundancy ChannelRedundancy CRCPresetLSB, CRCPresetMSB
Table 18-8: CRC-Coprocessor Parameters The CRC polynomial for the 8-bit CRC is fixed to x + x + x + x + 1 .
8 4 3 2
The CRC polynomial for the 16-bit CRC is fixed to x
16
+ x12 + x 5 + 1 .
18.7.2.3 Status Flags of the CRC-Coprocessor The status flag CRCReady indicates, that the CRC-Coprocessor has finished processing of all data bytes found in the FIFO buffer. With the CRCReady flag setting to 1, an interrupt is requested with TxIRq being set. This supports interrupt driven usage of the CRC-Coprocessor. When CRCReady and TxIRq are set to 1, respectively, the content of the CRCResultLSB- and CRCResultMSB-register and the flag CRCErr is valid. The CRCResultLSB- and CRCResultMSB-register hold the content of the CRC register, the CRCErr flag indicates CRC validity for the processed data.
18.8 Error Handling during Command Execution If any error is detected during command execution, this is shown by setting the status flag Err in the PrimaryStatus Register. For information about the cause of the error, the -Processor may evaluate the status flags in the ErrorFlag Register.
Error Flag of the ErrorFlag Register KeyErr AccessError FIFOOvl CRCErr FramingErr ParityErr CollErr Related to Command LoadKeyE2, LoadKey WriteE2, ReadE2, LoadConfig No specific commands Receive, Transceive, CalcCRC Receive, Transceive Receive, Transceive Receive, Transceive
Table 18-9: Error Flags Overview
134
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.9 MIFARE(R) Classic Security Commands 18.9.1 LOADKEYE2 COMMAND 0BHEX 18.9.1.1 Overview
Command LoadKeyE2 Codehex 0B Action Reads a key from the EPROM and puts it into the internal key buffer Arguments and Data Start Address LSB Start Address MSB
CL RC632
Returned Data -
The LoadKeyE2-Command interprets the first two bytes found in the FIFO buffer as EPROM starting byte-address. The EPROM bytes starting from the given starting byte-address are interpreted as key, stored in the correct key format as described in chapter 6.4.1. When all two argument-bytes are available in the FIFO buffer, the command execution starts. The LoadKeyE2-Command can be started only by the Processor. It stops automatically after having copied the key from the EPROM into the key buffer. 18.9.1.2 Relevant Error Flags for the LoadKeyE2-Command If the key format is not correct (see chapter 6.4.1) an undefined value is copied into the key buffer and the flag KeyError is set.
18.9.2 LOADKEY COMMAND 19HEX 18.9.2.1 Overview
Command LoadKey Codehex 19 Action Reads a key from the FIFO buffer and puts it into the key buffer Arguments and Data Byte0 (LSB) Byte1 ... Byte10 Byte11 (MSB) Returned Data -
The LoadKey-Command interprets the first twelve bytes it finds in the FIFO buffer as key, stored in the correct key format as described in chapter 6.4.1. When the twelve argument-bytes are available in the FIFO buffer they are checked and, if valid, are copied into the key buffer (see also 19.2). The LoadKey-Command can only be started by the -Processor. It stops automatically after having copied the key from the FIFO buffer into the key buffer. 18.9.2.2 Relevant Error Flags for the LoadKey-Command All bytes requested are copied from the FIFO buffer to the key buffer. If the key format is not correct (see chapter 6.4.1) an undefined value is copied into the key buffer and the flag KeyError is set.
135
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
18.9.3 AUTHENT1 COMMAND 0CHEX 18.9.3.1 Overview
Command Codehex Action Arguments and Data Card Auth-Command Card Block Address Card Serial Number LSB Card Serial Number Byte1 Card Serial Number Byte2 Card Serial Number MSB
CL RC632
Returned Data
Authent1
0C
Performs the first part of the Crypto1 (MIFARE Classic) card authentication
-
The Authent1-Command is a special Transceive-Command: it takes six argument bytes which are sent to the card. The card's response is not forwarded to the -Processor, but is used to check the authenticity of the card and to prove authenticity of the CL RC632 to the card. The Authent1-Command can be triggered only by the -Processor. The sequence of states for this command is the same as for the Transceive-Command (see 18.4.3). 18.9.4 AUTHENT2 COMMAND 14HEX 18.9.4.1 Overview
Command Authent2 Codehex 14 Action Performs the second part of the card authentication using the Crypto1 algorithm. Arguments and Data Returned Data -
The Authent2-Command is a special Transceive-Command. It does not need any argument byte but all necessary data which has to be sent to the card is assembled by the CL RC632 itself. The card response is not forwarded to the -Processor, but is used to check the authenticity of the card and to prove authenticity of the CL RC632 to the card. The Authent2-Command can only be started by the -Processor. The logical sequence for this command is the same as for the Transceive-Command (see 18.4.3). 18.9.4.2 Effect of the Authent2-Command If the Authent2-Command was successful, authenticity of card and CL RC632 is proved. In this case, the control bit Crypto1On is set automatically. When bit Crypto1On is set, all further card communication is done encrypted, using the Crypto1 security algorithm. If the Authent2-Command fails, bit Crypto1On is cleared. Note: The flag Crypto1On can not be set by the -Processor but only through a successfully performed Authent2-Command. The -Processor may clear the bit Crypto1On to continue with plain card communication. Note: The Authent2-Command has to be executed immediately after a successful Authent1-Command (see 18.9.3). Furthermore, the keys stored in the key buffer and those on the card have to match.
136
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
19 MIFARE CLASSIC AUTHENTICATION AND CRYPTO1
CL RC632
19.1 General The security algorithm implemented in MIFARE Classic products is called Crypto1. It is based on a proprietary stream cipher with a key length of 48 bits. To access data of a MIFARE Classic card, the knowledge of the according key is necessary. For successful card authentication and subsequent access to the card's data stored in the EEPROM, the correct key has to be available in the CL RC632. After a card is selected as defined in ISO14443A the user may continue with the MIFARE Classic protocol. In this case it is mandatory to perform a card authentication. The Crypto1 authentication is a 3-pass authentication. This procedure is done automatically with the execution of Authent1- (see 18.9.3) and the Authent2-Commands (see 18.9.4). During the card authentication procedure, the security algorithm is initialised. The communication with a MIFARE Classic card following a successful authentication is encrypted.
19.2 Crypto1 Key Handling During the authentication command the CL RC632 reads the key from the internal key buffer. The key is always taken from the key buffer. Therefore, the commands for Crypto1 authentication do not require addressing of a key. The user has to ensure, that the correct key is prepared in the key buffer before the card authentication is triggered. The key buffer can be loaded * * from the EPROM with the LoadKeyE2-Command (see 18.9.1) directly from the -Processor via the FIFO-Buffer with the LoadKey-Command (see 18.9.2)
This is shown in the following figure:
WriteE2
EPROM: Keys
From the Controller
FIFO LoadKey Key Buffer During Authent1 Serial Data Stream In (Plain) Crypto1 Module Serial Data Stream Out (Encrypted) LoadKeyE2
.
Figure 19-1: Key Handling: Block Diagram
137
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
19.3 Performing MIFARE Classic Authentication
CL RC632
To enable authentication of MIFARE Classic cards the Crypto1 security algorithm is implemented. To obtain valid authentication, the correct key has to be available in the key buffer of the CL RC632. Step 1: Load the internal key buffer by means of the LoadKeyE2- (see 18.9.1) or the LoadKey-Command (see 18.9.2). Step 2: Start the Authent1-Command (see 18.9.3). When finished, check the error flags to obtain the status of the command execution. Step 3: Start the Authent2-Command (see 18.9.4). When finished, check the error flags and bit Crypto1On to obtain the status of the command execution.
138
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
20 TYPICAL APPLICATION
CL RC632
20.1 Circuit Diagram The figure below shows a typical application, where the antenna is directly connected to the CL RC632:
DVDD
Reset
AVDD
TVDD
DVDD Control Lines -Processor Bus
RSTPD
AVDD
TVDD TX1
L0 C0
C1 C2a
Processor
Data Bus IRQ
TVSS
IRQ
CL RC632
TX2
L0
C0 C1
C2b C3
RX
R1
DVSS
OSCIN
OSCOUT AVSS
VMID
R2
13.56 MHz 15 pF 15 pF
C4 100 nF
Figure 20-1: Circuit Diagram for Application Example: Direct Matched Antenna
139
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
20.2 Circuit Description
CL RC632
The matching circuit consists of an EMC low pass filter (L0 and C0), a matching circuitry (C1 and C2), and a receiving circuit (R1, R2, C3 and C4), and the antenna itself. For more detailed information about designing and tuning an antenna please refer to the Application Note 'MIFARE and I CODE MICORE reader IC family; Directly Matched Antenna Design' and `MIFARE (14443A) 13,56 MHz RFID Proximity Antennas'.
20.2.1 EMC LOW PASS FILTER The MIFARE system operates at a frequency of 13.56 MHz. This frequency is generated by a quartz oscillator to clock the CL RC632 and is also the basis for driving the antenna with the 13.56 MHz energy carrier. This will not only cause emitted power at 13.56 MHz but will also emit power at higher harmonics. The international EMC regulations define the amplitude of the emitted power in a broad frequency range. Thus, an appropriate filtering of the output signal is necessary to fulfil these regulations. A multi-layer board it is recommended to implement a low pass filter as shown in the circuit above. The low pass filter consists of the components L0 and C0. The recommended values are given in the above mentioned application notes. Note: To achieve best performance all components shall have at least the quality of the recommended ones. Note: The layout has a major influence on the overall performance of the filter.
20.2.2 ANTENNA MATCHING Due to the impedance transformation of the given low pass filter, the antenna coil has to be matched to a certain impedance. The matching elements C1 and C2 can be estimated and have to be fine tuned depending on the design of the antenna coil. The correct impedance matching is important to provide the optimum performance. The overall Quality factor has to be considered to guarantee a proper ISO14443 communication scheme. Environmental influences have to considered as well as common EMC design rules. For details refer to the above mentioned application notes.
Note: Do not exceed the current limits ITVDD, otherwise the chip might be destroyed. Note: The overall 13.56MHz RFID proximity antenna design with the CL RC632 chip is straight forward and doesn't require a special RF-know how. However, all relevant parameters have to be considered to guarantee an overall optimum performance together with international EMC compliance.
140
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
20.2.3 RECEIVING CIRCUIT
CL RC632
The internal receiving concept of the CL RC632 makes use of both side-bands of the sub-carrier load modulation of the card response. No external filtering is required. It is recommended to use the internally generated VMID potential as the input potential of pin RX. This DC voltage level of VMID has to be coupled to the Rx-pin via R2. To provide a stable DC reference voltage a capacitance C4 has to be connected between VMID and ground. Considering the (AC) voltage limits at the Rx-pin the AC voltage divider of R1 + C3 and R2 has to be designed. Depending on the antenna coil design and the impedance matching the voltage at the antenna coil varies from antenna design to antenna design. Therefore the recommended way to design the receiving circuit is to use the given values for R1, R2, and C3 from the above mentioned application note, and adjust the voltage at the Rx-pin by varying R1 within the given limits.
Note: R2 is AC-wise connected to ground (via C4).
20.2.4 ANTENNA COIL The precise calculation of the antenna coils' inductance is not practicable but the inductance can be estimated using the following formula. We recommend designing an antenna either with a circular or rectangular shape.
l 1,8 L1 [nH ] = 2 l 1 [cm ] ln 1 - K N1 D1
l1 ............... Length of one turn of the conductor loop D1 ............. Diameter of the wire or width of the PCB conductor respectively K............... Antenna Shape Factor (K = 1,07 for circular antennas and K = 1,47 for square antennas) N1 ............. Number of turns ln .............. Natural logarithm function The actual values of the antenna inductance, resistance, and capacitance at 13.56 MHz depend on various parameters like: * * * * * antenna construction (Type of PCB) thickness of conductor distance between the windings shielding layer metal or ferrite in the near environment
Therefore a measurement of those parameters under real life conditions, or at least a rough measurement and a tuning procedure is recommended to guarantee the optimum performance. For details refer to the above mentioned application notes.
141
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
21 TEST SIGNALS
CL RC632
21.1 General The CL RC632 allows different kind of signal measurements. These measurements can be used to check the internally generated and received signals using the possibilities of the serial signal switch as described in chapter 15. Furthermore, with the CL RC632 the user may select internal analogue signals to measure them at pin AUX and internal digital signals to observe them on pin MFOUT by register selections. These measurements can be helpful during the design-in phase to optimise the receiver's behaviour or for test purpose.
21.2 Measurements Using the Serial Signal Switch Using the serial signal switch at pin MFOUT the user may observe data send to the card or data received from the card. The following tables give an overview of the different signals available.
SignalToMFOUT 0 0 0 0 0 0 0 0 1
MFOUTSelect 0 1 2 3 4 5 6 7 X
Signal routed to MFOUT pin LOW HIGH Envelope Transmit NRZ Manchester with Subcarrier Manchester RFU RFU Digital Test signal
Table 21-1 Signal routed to MFOUT pin Note: The routing of the Manchester and the Manchester with Subcarrier signal to the MFOUT is only possible at 106 kbaud according to ISO14443A.
142
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
21.2.1 TX-CONTROL The following plot shows as an example an ISO14443 A related communication.
CL RC632
The signal measured at MFOUT using the serial signal switch to control the data sent to the card .Setting the flag MFOUTSelect to 3 data sent to the card is shown NRZ coded. MFOUTSelect set to 2 shows the Miller coded signal. The RFOut signal is measured directly on the antenna showing the pulse shape of the RF signal. For detail information concerning the pulse of the RF signal please refer to the application note `MIFARE(R) Design of MF RC 500 Matching Circuits and Antennas'
MFOUTSelect =3 Serial data Stream 2V/Div.
MFOUTSelect =2 Serial data Stream 2V/Div.
RFout 1V/Div.
Figure 21 TX Control Signals
143
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
21.2.2 RX-CONTROL The following plot shows as an example an ISO14443 A related communication.
CL RC632
The following plot shows the beginning of a cards answer to a request signal. The signal RF shows the RF voltage measured directly on the antenna so that the cards load modulation is visible. MFOUTSelect set to 4 shows the Manchester decoded signal with subcarrier. MFOUTSelect set to 5 shows the Manchester decoded signal.
RF 1V/Div.
MFOUTSelect =4 Manchester with Subcarrier 2V/Div.
MFOUTSelect =5 Manchester 2V/Div.
Figure 22 RX Control Signals
144
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
21.3 Analog Test-Signals
CL RC632
The analog test signals may be routed to pin AUX by selecting them with the register bits TestAnaOutSel. Value 0 1 2 3 4 5 6 7 8 9 A B C D E F Signal Name Vmid Vbandgap VRxFollI VRxFollQ VRxAmpI VRxAmpQ VCorrNI VCorrNQ VCorrDI VCorrDQ VEvalL VEvalR VTemp rfu rfu rfu Voltage at internal node Vmid Internal reference voltage generated by the band gap. Output signal from the demodulator using the I-clock. Output signal from the demodulator using the Q-clock. I-channel subcarrier signal amplified and filtered. Q-channel subcarrier signal amplified and filtered. Output signal of N-channel correlator fed by the I-channel subcarrier signal. Output signal of N-channel correlator fed by the Q-channel subcarrier signal. Output signal of D-channel correlator fed by the I-channel subcarrier signal. Output signal of D-channel correlator fed by the Q-channel subcarrier signal. Evaluation signal from the left half bit. Evaluation signal from the right half bit. Temperature voltage derived from band gap. Reserved for future use Reserved for future use Reserved for future use Table 21-2: Analog Test Signal Selection Description
145
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
21.4 Digital Test-Signals
CL RC632
Digital test signals may be routed to pin MFOUT by setting bit SignalToMFOUT to 1. A digital test signal may be selected via the register bits TestDigiSignalSel in Register TestDigiSelect. The signals selected by a certain TestDigiSignalSel setting is shown in the table below:
TestDigiSignalSel F4hex E4hex D4hex C4hex B5hex A5hex 96hex 83hex E2hex 00hex Signal Name s_data s_valid s_coll s_clock rd_sync wr_sync int_clock BPSK_out BPSK_sig no test signal Data received from the card. Shows with 1, that the signals s_data and s_coll are valid. Shows with 1, that a collision has been detected in the current bit. Internal serial clock: during transmission, this is the coder-clock and during reception this is the receiver clock. Internal synchronised read signal (derived from the parallel -Processor interface). Internal synchronised write signal (derived from the parallel -Processor interface). Internal 13.56 MHz clock. BPSK signal output BPSK signal's amplitude detected output as defined by MFOUTSelect are routed to pin MFOUT. Description
Table 21-3: Digital Test Signal Selection
If no test signals are used, the value for the TestDigiSelect-Register shall be 00hex. Note: All other values of TestDigiSignalSel are for production test purposes only.
146
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
21.5 Examples of ISO14443A Analog- and Digital Test Signals
CL RC632
Fig. 22 shows a MIFARE Classic Card's answer to a request command using the Qclock receiving path. RX -Reference is given to show the Manchester modulated signal at the RX pin. This signal is demodulated and amplified in the receiver circuitry VRXAmpQ shows the amplified side band signal having used the QClock for demodulation. The signals VCorrDQ and VCorrNQ generated in the correlation circuitry are evaluated and digitised in the evaluation and digitizer circuitry. VEvalR and VEvalL show the evaluation signal of the right and left half bit. Finally, the digital test-signal S_data shows the received data which is send to the internal digital circuit and S_valid indicates that the received data stream is valid.
Figure 23. Receiving path Q-Clock
147
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
21.6 Examples of I*CODE1 Analog- and Digital Test Signals
CL RC632
Fig. 17 shows the answer of an I*CODE1 Label IC to a unselected read command using the Qclock receiving path. RX -Reference is given to show the Manchester modulated signal at the RX pin. This signal is demodulated and amplified in the receiver circuitry VRXAmpQ shows the amplified side band signal having used the QClock for demodulation. The signals VCorrDQ and VCorrNQ generated in the correlation circuitry are evaluated and digitised in the evaluation and digitizer circuitry. VEvalR and VEvalL show the evaluation signal of the right and left half bit. Finally, the digital test-signal S_data shows the received data which is send to the internal digital circuit and S_valid indicates that the received data stream is valid.
Receiving path Q-Clock
VrxAmpQ
VcorrDQ
VcorrNQ
VevalR
VevalL
Sdata
50sec/Dev.
SValid
500sec/Dev. Figure 24. Receiving path Q-Clock
148
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
22 ELECTRICAL CHARACTERISTICS
CL RC632
22.1 Absolute Maximum Ratings
SYMBOL Tamb,abs DVDD AVDD TVDD Vin,abs VRX,abs Absolute voltage on any digital pin to DVSS Absolute voltage on RX pin to AVSS -0.5 -0.5 DVDD + 0.5 AVDD + 0.5 V V DC Supply Voltages -0.5 6 V PARAMETER Ambient or Storage Temperature Range MIN -40 MAX +150 UNIT C
Table 22-1: Absolute Maximum Ratings 22.2 Operating Condition Range
SYMBOL Tamb DVDD AVDD TVDD PARAMETER Ambient Temperature Digital Supply Voltage Analog Supply Voltage Transmitter Supply Voltage CONDITIONS DVSS = AVSS = TVSS = 0V DVSS = AVSS = TVSS = 0V DVSS = AVSS = TVSS = 0V MIN -25 3.0 4.5 4.5 3.0 TYP +25 3.3 5.0 5.0 5.0 MAX +85 3.6 5.5 5.5 5.5 UNIT C V V V V
Table 22-2: Operating Condition Range 22.3 Current Consumption
SYMBOL PARAMETER CONDITIONS Idle Command IDVDD Digital Supply Current Stand By Mode Soft Power Down Mode Hard Power Down Mode Idle Command, Receiver On Idle Command, Receiver Off IAVDD Analog Supply Current Stand By Mode Soft Power Down Mode Hard Power Down Mode Continuous Wave ITVDD Transmitter Supply Current TX1 and TX2 unconnected TX1RFEn, TX2RFEn = 1 TX1 and TX2 unconnected TX1RFEn, TX2RFEn = 0 4.5 65 MIN TYP 6 3 800 1 25 8 6.5 1 1 MAX 9 5 1000 10 40 12 9 10 10 150 6 130 UNIT mA mA A A mA mA mA A A mA mA A
Table 22-3: Current Consumption
149
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
22.4 Pin Characteristics 22.4.1 INPUT PIN CHARACTERISTICS
CL RC632
Pins D0 to D7, A0, and A1 have TTL input characteristics and behave as defined in the following table.
SYMBOL ILeak VT PARAMETER Input Leakage Current Threshold CMOS: DVDD < 3.6 V TTL: 4.5 < DVDD CONDITIONS MIN -1.0 0.35 DVDD 0.8 MAX +1.0 0.65 DVDD 2.0 UNIT A V V
Table 22-4: Standard Input Pin Characteristics
The digital input pins NCS, NWR, NRD, ALE, A2, and MFIN have Schmitt-Trigger characteristics, and behave as defined in the following table.
SYMBOL ILeak VT+ PARAMETER Input Leakage Current Positive-Going Threshold TTL: 4.5 < DVDD CMOS: DVDD < 3.6 V TTL: 4.5 < DVDD CMOS: DVDD < 3.6 V CONDITIONS MIN -1.0 1.4 0.65 DVDD 0.8 0.25 DVDD MAX +1.0 2.0 0.75 DVDD 1.3 0.4 DVDD UNIT A V V V V
VT-
Negative-Going Threshold
Table 22-5: Schmitt-Trigger Input Pin Characteristics Pin RSTPD has Schmitt-Trigger CMOS characteristics. In addition, it is internally filtered with an RC-lowpass filter, which causes a relevant propagation delay for the reset signal:
SYMBOL ILeak VT+ VTtRSTPD,p PARAMETER Input Leakage Current Positive-Going Threshold Negative-Going Threshold Propagation Delay CMOS: DVDD < 3.6 V CMOS: DVDD < 3.6 V CONDITIONS MIN -1.0 0.65 DVDD 0.25 DVDD MAX +1.0 0.75 DVDD 0.4 DVDD 20 UNIT A V V s
Table 22-6: RSTPD Input Pin Characteristics The analog input pin RX has the following input capacitance:
SYMBOL CRX PARAMETER Input Capacitance CONDITIONS MIN MAX 15 UNIT pF
Table 22-7: RX Input Capacitance The analog input pin RX has the following input voltage range:
SYMBOL VIN,RX PARAMETER Dynamical Voltage input range CONDITIONS AVDD=5V, T=25C MIN 1,1V MAX 4,4 UNIT V
Table 22-8: RX Input voltage range
150
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
22.4.2 DIGITAL OUTPUT PIN CHARACTERISTICS
CL RC632
Pins D0 to D7, MFOUT and IRQ have CMOS output characteristics and behave as defined in the following table.
SYMBOL VOH PARAMETER Output Voltage HIGH CONDITIONS DVDD = 5 V, IOH = -1 mA DVDD = 5 V, IOH = -10 mA DVDD = 5 V, IOL = 1 mA DVDD = 5 V, IOL = 10 mA DVDD = 5 V MIN 2.4 2.4 TYP 4.9 4.2 25 250 400 400 10 MAX UNIT V V mV mV mA
VOL IO
Output Voltage LOW Output Current source or sink
Table 22-8: Digital Output Pin Characteristics Note: IRQ pin may also be configured as open collector. In that case the values for VOH do not apply.
22.4.3 ANTENNA DRIVER OUTPUT PIN CHARACTERISTICS The source conductance of the antenna driver pins TX1 and TX2 for driving the HIGH level can be configured via GsCfgCW in the CwConductance Register, while their source conductance for driving the LOW level is constant. For the default configuration, the output characteristic is specified below:
SYMBOL VOH PARAMETER Output Voltage HIGH CONDITIONS TVDD = 5.0 V, IOL = 20 mA TVDD = 5.0 V, IOL = 100 mA TVDD = 5.0 V, IOL = 20 mA TVDD = 5.0 V, IOL = 100 mA Continuous Wave MIN TYP 4.97 4.85 30 150 200 MAX UNIT V V mV mV mApeak
VOL ITX
Output Voltage LOW Transmitter Output Current
Table 22-9: Antenna Driver Output Pin Characteristics
151
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
22.5 AC Electrical Characteristics 22.5.1 AC SYMBOLS
CL RC632
Each timing symbol has five characters. The first character is always 't' for time. The other characters indicate the name of a signal or the logic state of that signal (depending on position):
Designation: A D W R L C S Signal: address data NWR or nWait NRD or R/NW or nWrite ALE or AS NCS NDS or nDStrb and nAStrb, SCK Designation: H L Z X V N Logic Level: HIGH LOW high impedance any level or data any valid signal or data NSS
Example: tAVLL = time for address valid to ALE low
152
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
22.5.2 AC OPERATING SPECIFICATION 22.5.2.1 Bus Timing for Separated Read/Write Strobe
SYMBOL tLHLL tAVLL tLLAX tLLWL tCLWL tWHCH tRLDV tRHDZ tWLDV tWHDX tWLWH tAVWL tWHAX tWHWL PARAMETER ALE pulse width Multiplexed Address Bus valid to ALE low (Address Set Up Time) Multiplexed Address Bus valid after ALE low (Address Hold Time) ALE low to NWR, NRD low NCS low to NRD, NWR low NRD, NWR high to NCS high NRD low to DATA valid NRD high to DATA high impedance NWR low to DATA valid DATA hold after NWR high (Data Hold Time) NRD, NWR pulse width Separated Address Bus valid to NRD, NWR low (Set Up Time) Separated Address Bus valid after NWR high (Hold Time) period between sequenced read / write accesses 8 65 30 8 150 MIN 20 15 8 15 0 0 65 20 35
CL RC632
MAX
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 22-10: Timing Specification for Separated Read/Write Strobe
tLHLL
ALE
tCLWL
tWHCH
NCS
tLLWL tWHWL tWLWH tWHWL
NWR NRD
tWLDV tRLDV tWHDX tRHDZ
tAVLL
tLLAX
D0 ... D7
Multiplexed Addressbus
A0 ... A2
tAVWL
D0 ... D7
tWHAX
A0 ... A2
Separated Addressbus
A0 ... A2
Figure 22-1: Timing Diagram for Separated Read/Write Strobe
Note: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don't care. For the multiplexed address and data bus the address lines A0 to A2 have to be connected as described in 4.3.
153
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
22.5.2.2 Bus Timing for Common Read/Write Strobe
SYMBOL tLHLL tAVLL tLLAX tLLSL tCLSL tSHCH tSLDV,R tSHDZ tSLDV,W tSHDX tSHRX tSLSH tAVSL tSHAX tSHSL tRVSL PARAMETER AS pulse width Multiplexed Address Bus valid to AS low (Address Set Up Time) Multiplexed Address Bus valid after AS low (Address Hold Time) AS low to NDS low NCS low to NDS low NDS high to NCS high NDS low to DATA valid (for read cycle) NDS low to DATA high impedance (read cycle) NDS low to DATA valid (for write cycle) DATA hold after NDS high (write cycle, Hold Time) R/NW hold after NDS high NDS pulse width Separated Address Bus valid to NDS low (Hold Time) Separated Address Bus valid after NDS high (Set Up Time) period between sequenced read/write accesses R/NW valid to NDS low MIN 20 15 8 15 0 0 MAX
CL RC632
65 20 35 8 8 65 30 8 150 8
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 22-11: Timing Specification for Common Read/Write Strobe
tLHLL
ALE
tCLSL
tSHCH
NCS
tRVSL
tSHRX
R/NW
tLLSL tSHSL tSLSH tSHSL
NDS
tAVLL
tLLAX
tSLDV,R tSLDV,W
tSHDX tSHDZ
D0 ... D7
Multiplexed Addressbus
A0 ... A2
tAVSL
D0 ... D7
tSHAX
A0 ... A2
Separated Addressbus
A0 ... A2
Figure 22-2: Timing Diagram for Common Read/Write Strobe
Note: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don't care. For the multiplexed address and data bus the address lines A0 to A2 have to be connected as described in 4.3.
154
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
22.5.2.3 Bus Timing for EPP
SYMBOL tLLLH tAVLH tLHAX tCLSL tSHCH tSLDV,R tSHDZ tSLDV,W tSHDX tSHRX tSLSH tRVSL tSLWH tSHWL PARAMETER nAStrb pulse width Multiplexed Address Bus valid to nAStrb high (Set Up Time) Multiplexed Address Bus valid after nAStrb high (Hold Time) NCS low to nDStrb low nDStrb high to NCS high nDStrb low to DATA valid (read cycle) nDStrb low to DATA high impedance (read cycle) nDStrb low to DATA valid (write cycle, Set up Time) DATA hold after nDStrb high (write cycle, Hold Time) nWrite hold after nDStrb high nDStrb pulse width nWrite valid to nDStrb low nDStrb low to nWait high nDStrb high to nWait low 8 8 65 8 75 75 MIN 20 15 8 0 0 65 20 35 MAX
CL RC632
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 22-12: Timing Specification for Common Read/Write Strobe
tCLSL
tSHCH
NCS
tRVSL
tSHRX
nWrite
tSLSH
nDStrb nAStrb
tSLDV,R tSLDV,W tSHDX tSHDZ
D0 ... D7
D0 ... D7 A0 ... A7
tSLWH
tSHWL
nWait
Figure 22-3: Timing Diagram for Common Read/Write Strobe
Remark: The figure does not distinguish between the Address Write Cycle and a Data Write Cycle. Take in account, that timings for the Address Write and Data Write Cycle are different. For the EPP-Mode the address lines A0 to A2 have to be connected as described in 4.3.
155
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
22.5.2.4 Timing for SPI compatible interface
SYMBOL tSCKL tSCKH tSHDX tDXSH tSLDX tSLNH PARAMETER SCK low pulse width SCK high pulse width SCK high to data changes data changes to SCK high SCK low to data changes SCK low to NSS high MIN 100 100 20 20 20 MAX
CL RC632
15
UNIT ns ns ns ns ns ns
Table 22-13 Timing Specification for SPI
tSCKL
tSCKH
tSCKL
SCK
tSLDX tDXSH tSHDX tDXSH
MOSI
MSB
LSB
MISO
MSB
LSB
tSLNH
NSS
Figure 22 Timing Diagram for SPI Note: To send more than bytes in one datastream the NSS signal has to low all the time. To send more than one datastream NSS has to be set to HIGH level in between the datastreams.
156
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
22.5.3 CLOCK FREQUENCY The clock input is pin 1, OSCIN.
PARAMETER Clock Frequency (checked by the clock filter) Duty Cycle of Clock Frequency Jitter of Clock Edges SYMBOL fOSCIN dFEC tjitter 40 MIN TYP 13.56 50
CL RC632
MAX
UNIT MHz
60 10
% ps
The clock applied to the CL RC632 acts as time basis for the coder and decoder of the synchronous system. Therefore stability of clock frequency is an important factor for proper performance. To obtain highest performance, clock jitter shall be as small as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry (see 12).
157
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
23 EPROM CHARACTERISTICS
CL RC632
The EPROM has a size of 32x16x8 = 4.096 bit.
SYMBOL tEEEndurance tEERetention tEEErase tEEWrite PARAMETER Data Endurance Data Retention Erase Time Write Time Tamb 55C CONDITIONS MIN 100.000 10 2.9 2.9 MAX UNIT erase/write cycles years ms ms
Table 23-1:EPROM Characteristics
158
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
24 ESD SPECIFICATION
CL RC632
To ensure the usage of the CL RC632 during production the ICs is specified as described in the following table. TEST ESDH ESDM NAME ESD Susceptibility (Human body model) ESD Susceptibility (Machine model) CONDITIONS 1500 , 100 pF 0.75 H, 200 pF 1 kV 100 V MAX
Table 24-1. ESD Specification
159
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
25 PACKAGE OUTLINES
CL RC632
25.1 SO32
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A
X
c y HE vM A
Z 32 17
Q A2 pin 1 index A1 (A3 ) Lp 1 e bp 16 wM L detail X A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. A1 A2 A3 bp c D(1) E(1) e HE L mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 10.65 1.27 10.00 1.4
Lp 1.1 0.4
Q 1.2 1.0
v 0.25
w 0.25
y 0.1
Z (1) 0.95 0.55
8o 0o
inches 0.10 0.012 0.096 0.01 0.004 0.086
0.02 0.011 0.81 0.01 0.007 0.80
0.30 0.419 0.043 0.047 0.01 0.055 0.050 0.29 0.394 0.016 0.039
0.037 0.01 0.004 0.022
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT287-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-25 97-05-22
Figure 255-1: Outline and Dimension of CL RC632 in SO32
160
Confidential
Philips Semiconductors
Product Specification Rev. 3.0; May 2003
Multiple Protocol Contactless Reader IC
Definitions
CL RC632
Data sheet status Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics section of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. This data sheet contains final product specifications.
26
DISCLAIMERS
26.1 Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so on their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
26.2 Licence Policy Purchase of this Philips IC with a functionally according to ISO/IEC 15693 Standard does not convey an implied license under any patent right on this standard. A license for the Philips portfolio of patents on the ISO/IEC 15693 Standard can be obtained via the Philips Intellectual Property and Standards department. For more information please contact the nearest Philips Semiconductors sales office.
161
Confidential
27
REVISION HISTORY
27.1 Update from Revision 2.0 to Revision 3.0 The whole document was editorial revised. New phrasings and additional descriptions have been added. The table below refers to relevant changes in content.
Chapter 5.2.4.2 22.4.1 Added Bits 4-3: `ISO Selection' Chapter `Input Pin characteristics': dynamical input voltage range for RX pin added Description
Table 0-1: Update from Revision 2.0 to Revision 3.0
27.2 Versions Up to Revision 3.0
REVISION 3.0 2.0 1.0 DATE November2002 June 2002 January2002 CPCN PAGE DESCRIPTION first published version second published version internal version
Table 0-2: Document Revision History
Philips Semiconductors - a worldwide company
Contact Information For additional information please visit http://www.semiconductors.philips.com.Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
SCA74
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without any notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
P h i li p s S e m ic o n d u c t o r s

▲Up To Search▲

Price & Availability of CLRC632

	To Download CLRC632 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .